International Conference on Engineering Education – ICEE 2007 Bringing Research Issues into Lab Scenarios on the Example of SoC Testing

Abstract- A conception and a teaching/learning environment is presented to improve the teaching quality in the field of system on chip design and test. Both, gate level and register transfer level test and design for testability problems are covered. In this environment, different embedded built-in self-test architectures and their quality can be evaluated by fault simulation. Since plain low-level methods in this field have lost their importance, hierarchical approaches are supported by this environment. The system supports distance learning as well as a web-based computer-aided teaching. The interactive modules are focused on easy action and reaction, learning by doing, a game-like use, and on encouraging students for critical thinking, problem solving, and creativity. Index Terms – computer-aided teaching, distance learning, research-oriented learning, digital systems, system-on-chip, design and test, built-in self-test, gate and register transfer levels, hierarchical approaches