Soft scheduling for hardware

Abstract. Hardware designs typically combine parallelism and resource-sharing; a circuit's correctness relies on shared resources being accessed mutually exclusively. Conventional high-level synthesis systems guaran-tee mutual exclusion by statically serialising access to shared resources during a compile-time process called scheduling. This approach suers from two problems: (i) there is a large class of practical designs which cannot be scheduled statically; and (ii) a statically xed schedule re-moves some opportunities for parallelism leading to less ecient circuits. This paper surveys the expressivity of current scheduling methods and presents a new approach which alleviates the above problems: rst schedul-ing logic is automatically generated to resolve contention for shared re-sources dynamically; then static analysis techniques remove redundant scheduling logic. We call our method Soft Scheduling to highlight the analogy with Soft Typing: the aim is to retain the exibility of dynamic scheduling whilst using static analysis to remove as many dynamic checks as possible.