In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire reconnection simultaneously. To accomplish this, we intro-duce a new logic representation that implements all possible wire reconnections implicitly by enhancing global flow op-timization techniques. Since our method takes into account circuit transformation during routing phase where the accu-rate physical information is available, we can obtain better results than the conventional routing algorithms. In addi-tion, we can succeed in routing even if other routers like rip-up and reroute methods fail. The algorithm has been im-plemented and the experimental results are p...
[[abstract]]©2001 IEICE-The single wire replacement attempts to replace a target wire by another wir...
This paper describes a three-layer maze router for chip-planning applications. The router contains a...
[[abstract]]In this paper, we propose a layout-driven synthesis approach for field programmable gate...
In this paper, we propose a new methodology to inte-grate multiple circuit tranformations and routin...
In this paper, we present a new method to improve global routing results. By using an amplified cong...
A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of ...
[[abstract]]Global flow optimization (GFO) can perform multiple fanout/fanin wire reconnections at a...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
In circuit-switched networks it is well known that dynamic rout- ABSTRACT ing can provide significan...
177 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.In this thesis, we study an a...
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becom...
Abstract—The most popular algorithm for solving the routing problem for field programmable gate arra...
A method for performing global routing on an integrated circuit design is disclosed. The integrated ...
Abstract- With the exponential reduction in scaling of feature size, inter-wire coupling capacitance...
[[abstract]]©2001 IEICE-The single wire replacement attempts to replace a target wire by another wir...
This paper describes a three-layer maze router for chip-planning applications. The router contains a...
[[abstract]]In this paper, we propose a layout-driven synthesis approach for field programmable gate...
In this paper, we propose a new methodology to inte-grate multiple circuit tranformations and routin...
In this paper, we present a new method to improve global routing results. By using an amplified cong...
A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of ...
[[abstract]]Global flow optimization (GFO) can perform multiple fanout/fanin wire reconnections at a...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
In circuit-switched networks it is well known that dynamic rout- ABSTRACT ing can provide significan...
177 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.In this thesis, we study an a...
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becom...
Abstract—The most popular algorithm for solving the routing problem for field programmable gate arra...
A method for performing global routing on an integrated circuit design is disclosed. The integrated ...
Abstract- With the exponential reduction in scaling of feature size, inter-wire coupling capacitance...
[[abstract]]©2001 IEICE-The single wire replacement attempts to replace a target wire by another wir...
This paper describes a three-layer maze router for chip-planning applications. The router contains a...
[[abstract]]In this paper, we propose a layout-driven synthesis approach for field programmable gate...