The Performance Potential for Single Application Heterogeneous Systems∗

A consideration of Amdahl’s Law [9] suggests a single-chip multiprocessor with asymmetric cores is a promising way to improve performance [16]. In this paper, we conduct a limit study of the potential benefit of the tighter integration of a fast sequential core de-signed for instruction level parallelism (e.g., an out-of-order superscalar) and a large number of smaller cores designed for thread-level parallelism (e.g., a graphics processor). We optimally schedule instructions across cores under assumptions used in past ILP limit studies. We measure sensitivity to the sequential performance (instruction read-after-write latency) of the low-cost parallel cores, and latency and bandwidth of the com-munication channel between these cores and the fast sequential core. We find that the potential speedup of traditional “general purpose ” applications (e.g., those from SpecCPU) as well as a heterogeneous workload (game physics) on a CPU+GPU system is low (2.2× to 12.7×), due to poor sequential performance of the parallel cores. Communication latency and bandwidth have comparatively small performance impact (1.07 × to 1.48×) calling into question whether integrating onto one chip both an array of small parallel cores and a larger core will, in practice, benefit the performance of these workloads significantly when compared to a sys-tem using two separate specialized chips.