Mapping array communication onto fifo communication – towards an implementation

In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the imple-mentation of such applications is mostly FIFO-based. Map-ping array communication onto a FIFO-based implementa-tion requires complex address generators if the arrays have multiple dimensions. In this paper, we present a method for mapping array communication onto an efficient micro-computer architecture implementation based on FIFO com-munication via shared memory. A good hardware/software partitioning for the address generation is proposed. Fur-thermore, a complete design flow from specification to im-plementation is described. We illustrate this method with a design case: the communication of video frames between the frontend and the compressor in an MPEG encoder. 1