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to interconnect resistance. Although timing can often be solved by this means, other problems can be created in the process. ear resistor model for the transistors. The delay calculation is based onfirst order approximations, such as Elmore delay or Sakurai’s expres-sion. These models are of limited accuracy even when only RC delay is concerned, but are futile for RCL interconnects and crosstalk, delay uncertainty, and signal integrity problems. Therefore, a system planner based on the conventional delay-driven, wire-by-wire planning paradigm can not guarantee the reliability or feasibility of the synthesized communication links. It also lacks th