Interconnect-driven floorplanning with fast global wiring planning and optimization

This paper presents an interconnect-driven floorplanning (IDFP) flow and algorithm integrated with multi-layer global wiring plan-ning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topol-ogy optimization, layer assignment, buffer insertion, wire siz-ing and spacing. It also includes fast routability estimation and performance-driven routing for congestion control. Our experi-ments on the SUN picoJava-IITM core test circuit show that over 74 % delay reduction can be achieved using our interconnect-driven floorplanner, compared to a conventional floorplanner without con-sideration of interconnect performance optimization/planning. We expect that IDFP with GWP will play a central role in designing interconnect-limiting, high-performance integrated circuits.