Simultaneous optimization of delay and number of operations in multiplierless implementation of linear systems

Many optimization techniques exist for the hardware implementation of multiplierless linear systems. These methods mainly reduce the number of additions and subtractions by eliminating common subexpressions. These optimizations can increase the critical path of the computations, which is unacceptable for high performance systems. In this work, we present a technique that controls the delay during the optimization. To the best of our knowledge this is the only technique that achieves the best possible delay and at the same time finds all possible common subexpressions. Furthermore our technique can be applied to linear systems consisting of any number of variables. We achieve an average of 50 % fewer operations for the same delay, over a method that extracts only non-recursive common subexpressions. Index Terms – delay optimization, common subexpression elimination, DSP transforms, multiplierless filters, logic synthesi