Lowpower data forwarding for vliw embedded architectures

Abstract—In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) pro-cessor architectures based on the forwarding (or bypassing) hard-ware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimiza-tion technique exploits the forwarding paths to avoid the power cost of writing/reading short-lived variables to/from the register file (RF). Such optimization is justified by the fact that, in appli-cation-specific embedded systems, a significant number of vari-ables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived vari-ables can thus be accessed directly through the forwarding regis-ters, avoiding writeback to the RF by the producer instruction and successive read from the RF by the consumer instruction. The de-cision concerning the enabling of the RF writeback phase is taken at compile time by the compiler static scheduling algorithm. This approach implies a minimal overhead on the complexity of the pro-cessor control logic and, thus, no critical path increase. The ap-plication of the proposed solution to a VLIW embedded core has shown an average RF power saving of 7.8 % with respect to the un-optimized approach on the given set of target benchmarks (patent pending owned by ST Microelectronics). Index Terms—Low-power design, microprocessors, VLSI design