Abstract—In this paper, we describe the design of on-chip re-peater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18- m CMOS process is described and measured. Index Terms—High-speed integrated circuits, integrated circui
This paper describes a low-power synchronous pulsed signaling scheme on a fully ac coupled multidrop...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...
High-performance long-range NoC link enables efficient implementation of network-on-chip topologies ...
In this paper, we describe the design of on-chip repeaterless interconnects with nearly speed-of-lig...
Abstract—An asynchronous high-speed wave-pipelined bit-se-rial link for on-chip communication is pre...
The propagation limits of electrical signals for systems built with conventional silicon processing ...
As VLSI progresses into Very Deep Submicron (VDSM) realms, global interconnects play an increasingly...
Global on-chip interconnects are a limiting factor in modern high performance VLSI systems due to cr...
Abstract—This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed ...
A bidirectional serial link on-chip implementation is going to be assessed so as to set the option o...
Abstract—We propose a novel cost-effective long-range NoC in-terconnect design based on current-mode...
Abstract—Pulse-based data transmission has been demon-strated as a power-saving and high performance...
The performance of many digital systems today is limited by the interconnection bandwidth between ch...
We propose circuits for low power high throughput multilevel current mode signaling using 2 bit simu...
Global on-chip data communication is becoming a concern as the gap between transistor speed and inte...
This paper describes a low-power synchronous pulsed signaling scheme on a fully ac coupled multidrop...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...
High-performance long-range NoC link enables efficient implementation of network-on-chip topologies ...
In this paper, we describe the design of on-chip repeaterless interconnects with nearly speed-of-lig...
Abstract—An asynchronous high-speed wave-pipelined bit-se-rial link for on-chip communication is pre...
The propagation limits of electrical signals for systems built with conventional silicon processing ...
As VLSI progresses into Very Deep Submicron (VDSM) realms, global interconnects play an increasingly...
Global on-chip interconnects are a limiting factor in modern high performance VLSI systems due to cr...
Abstract—This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed ...
A bidirectional serial link on-chip implementation is going to be assessed so as to set the option o...
Abstract—We propose a novel cost-effective long-range NoC in-terconnect design based on current-mode...
Abstract—Pulse-based data transmission has been demon-strated as a power-saving and high performance...
The performance of many digital systems today is limited by the interconnection bandwidth between ch...
We propose circuits for low power high throughput multilevel current mode signaling using 2 bit simu...
Global on-chip data communication is becoming a concern as the gap between transistor speed and inte...
This paper describes a low-power synchronous pulsed signaling scheme on a fully ac coupled multidrop...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...
High-performance long-range NoC link enables efficient implementation of network-on-chip topologies ...