Frame-level pipelined motion estimation array processor

Abstract—A systolic motion estimation processor (MEP) core architecture implementing the full-search block-matching (FSBM) algorithm is presented. A unique feature of this MEP architecture is its support of frame-level pipelined operation. As such, it is pos-sible to process pixels from consecutive frames without any pro-cessor idle time. It is designed so that no data broadcasting opera-tions are required, and achieves 100 % fully pipelined computation. It compares favorably with existing MEP architectures in terms of both performance and complexity of architecture. Index Terms—Block matching, frame-level pipeline, full search, motion estimation, VLSI architecture. I