An Efficient Programmable 10 Gigabit Ethernet Network Interface Card

This paper explores the hardware and software mech-anisms necessary for an efficient programmable 10 Giga-bit Ethernet network interface card. Network interface pro-cessing requires support for the following characteristics: a large volume of frame data, frequently accessed frame metadata, and high frame rate processing. This paper pro-poses three mechanisms to improve programmable network interface efficiency. First, a partitioned memory organiza-tion enables low-latency access to control data and high-bandwidth access to frame contents from a high-capacity memory. Second, a novel distributed task-queue mecha-nism enables parallelization of frame processing across many low-frequency cores, while using software to main-tain total frame ordering. Finally, the addition of two new atomic read-modify-write instructions reduces frame order-ing overheads by 50%. Combining these hardware and soft-ware mechanisms enables a network interface card to satu-rate a full-duplex 10 Gb/s Ethernet link by utilizing 6 pro-cessor cores and 4 banks of on-chip SRAM operating at 166 MHz, along with external 500 MHz GDDR SDRAM. 1