VLSI ARCHITECTURE OF THE RECONFIGURABLE COMPUTING ENGINE FOR DIGITAL SIGNAL PROCESSING APPLICATIONS

In this paper, a novel reconfigurable computing engine for digi-tal signal processing applications is proposed. The kernel compo-nent of the reconfigurable computing (RC) engine is the general-purpose processing cluster (GPPC) array, which is constructed of the GPPCs, as an MIMD model to achieve high flexibility for map-ping applications and algorithms to the RC engine. GPPC per-forms the data-parallelism operations efficiently using the SIMD insturctions. Therefore, GPPC can not only execute the 32-bit op-erations but also perform 4-way 8-bit operations or 2-way 16-bit operations simultaneously. For the efficient connectivity, the inter-GPPC-row reconfigurable network is also proposed to achieve the requirements of high flexibility, low complexity, small area and short network delay. 1