Algorithms, Design

We propose an interconnect reorganization algorithm for re-duction stages in parallel multipliers. It aims at minimiz-ing power consumption for given static probabilities at the primary inputs. In typical signal processing applications the transition probability varies between the most and least significant bits. The same is the case for individual sig-nals within the multiplier. Our interconnect reorganization exploits this to reduce the overall switching activity, thus reducing the multiplier’s power consumption. We have de-veloped a CAD tool that reorganizes the connections within the multiplier architecture in an optimized way. Since the applied heuristic requires power estimation, we have also developed a very fast estimator fine tuned for parallel mul-tipliers. The CAD tool automatically generates gate-level VHDL code for the optimized multipliers. This code and code for unoptimized multipliers have been compared using state of the art power estimation tools. The reduction in power consumption ranges from 7 % up to 23 % and can be achieved without any noticeable overhead in performance and area. Categories and Subject Descriptor