A Flexible Thread Scheduler for Hierarchical Multiprocessor Machines

With the current trend of multiprocessor machines towards more and more hierarchical architectures, exploiting the full computational power requires careful distribution of exe-cution threads and data so as to limit expensive remote memory accesses. Existing multi-threaded libraries provide only limited facilities to let applications express distribu-tion indications, so that programmers end up with explic-itly distributing tasks according to the underlying architec-ture, which is difficult and not portable. In this article, we present: (1) a model for dynamically expressing the struc-ture of the computation; (2) a scheduler interpreting this model so as to make judicious hierarchical distribution deci-sions; (3) an implementation within the Marcel user-level thread library. We experimented our proposal on a scientific application running on a ccNUMA Bull NovaScale with 16 Intel Itanium II processors; results show a 30 % gain compared to a classical scheduler, and are similar to what a handmade scheduler achieves in a non-portable way. 1