Scaling constraints in nanoelectronic random access memories

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F2) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10 % readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 × 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 × 512. 1