Interconnect Tuning Strategies for High Performance ICs

Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spac-ings in multi-layer interconnect to simultaneously optimize signal dis-tribution, signal performance, signal integrity, and interconnect manu-facturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tun-ing in the literature. We center on global wiring layers and intercon-nect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We ad-dress four basic questions. (1) How should width and spacing be allo-cated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circum-stances are shield wires the optimum technique for improving intercon-nect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30 % in current technologies.