The vector floating-point unit in a synergistic processor element of a CELL processor

toshiba.co.jp The floating-point unit in the Synergistic Processor El-ement of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and integer operations and 2-way SIMD double precision operations. The design required a high-frequency, low la-tency, power and area efficiency with primary application to the multimedia streaming workloads, such as 3D graph-ics. The FPU has 3 different latencies, optimizing the per-formance critical single precision FMA operations, which are executed with a 6-cycle latency at an 11FO4 cycle time. The latency includes the global forwarding of the result. These challenging performance, power, and area goals were achieved through the co-design of architecture and im-plementation with optimizations at all levels of the design. This paper focuses on the logical and algorithmic aspects of the FPU we developed, to achieve these goals.