LATERAL POWER MOSFET WITH AN IMPROVED ON-RESISTANCE

The-product of the on-resistance by the area of the high-voltage, LDMOS transistor can be reduced by a factor of two to four by creating a surface accumulation layer along the surface of the drift region. This surface accumulation region exists only in the on state of the device. It can be created by using a semi-insulating layer over a thin field oxide layer covering the drift region, or alternatively via a fourth electrode located between the drain and the gate, and held at a constant high voltage. Henceforth, a simple LDMOST structure with no critical processing steps, low on-resistance and high breakdown voltage is claimed. 1