A 300MS/s 14-bit digital-to-analog converter in logic CMOS

Abstract—We describe a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18- m CMOS logic processes. We trim the static inte-gral nonlinearity to 0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm2 of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s. Index Terms—Digital-to-analog conversion, floating gate. I