Process Variation Characterization of Chip-Level Multiprocessors

Within-die variation in leakage power consumption is sub-stantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this prob-lem via conservative assumptions is sub-optimal. Instead, op-erating systems may adapt task assignment and power man-agement decisions to the variable characteristics of cores, im-proving system-wide power consumption and performance. Researchers have proposed such adaptation techniques. How-ever, they rely on knowledge of CMP process variation (PV) maps. These maps are not provided by processor vendors, providing them would impose additional cost during the test-ing process, and static maps would not permit adaptation to aging effects. Further progress on developing and validating PV aware control techniques for CMPs requires access to PV maps for real processors. We present an online technique to extract the PV maps of CMPs. Potentially automatic tem-perature measurements with built-in on-die sensors during the execution of characterization workloads are used to determine variation in leakage power consumption. The proposed tech-nique is applied to real CMPs, and the resulting PV maps are used within a PV aware task assignment and scheduling algorithm