Exploring the design space of power-aware opto-electronic networked systems

As microprocessors become increasingly intercon-nected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increasing, optical links are replacing electrical links in inter-chassis and inter-board environments. As a re-sult, the power dissipation of optical links is becoming as critical as their speed. In this paper, we first explore op-tions for building high speed opto-electronic links and discuss the power characteristics of different link components. Then, we propose circuit and network mechanisms that can realize power-aware optical links – links whose power consumption can be tuned dynamically in response to changes in network traffic. Finally, we incorporate power-control policies along with the power characterization of link circuitry into a de-tailed network simulator to evaluate the performance cost and power savings of building power-aware opto-electronic net-worked systems. Simulation results show that more than 75% savings in power consumption can be achieved with the pro-posed power-aware opto-electronic network.