Incremental exploration of the combined physical and behavioral design space

Achieving design closure is one of the biggest headaches for mod-ern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly important factors such as the impact of interconnect on the area and power consump-tion of integrated circuits. Bringing physical information up into the logic level or even behavioral-level stages of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level synthesis system. This sys-tem integrates high-level and physical design algorithms to con-currently improve a system’s schedule, resource binding, and floor-plan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplan-ners for physical estimation, this approach has the benefit of effi-ciency, stability, and better quality of results. For designs contain-ing functional units with non-unity aspect ratios, the average CPU time improved by 369%, the area improved by 14.24%, and power improved by 4%