Throughput Driven Unidirectional Bus Design for NoC Applications

Abstract At the physical layer of Network-on-Chip (NoC) implementations, blocks and switches are already as-signed and inter block connections have to be planned. Most of the inter block connections will consist of a large number of long parallel wires. Such wires usually have signicant re-sistance and (coupling as well as self) capacitance. As such, these wires may severely limit the achievable performance. The performance may (and usually is) improved by buffer-ing, i.e. the insertion of restoring electronics to avoid the quadratic dependence (caused by the product of r and c per unit length) of the delay on wire length. The main contribution of this paper is in providing an optimization approach for the throughput on such buffered NoC wires. By extending our work of [2], we provide a methodology to optimize the throughput under buffer area constraints. It appears that in that case the highest through-put can be obtained using sub-maximal density congura-tions with greater than minimum wire spacing and width. Moreover, the results show that a signicant saving on Si area for buffering need only cost a moderate decrease of throughput. For example, a specic experiment for a 0:18µm technology yields 90 % of the absolute maximum throughput using only 30 % of the corresponding buffer area. I