Efficient Analysis and Optimization of ESD Protection Circuits

Electrostatic Discharge (ESD) is generally recognized as an increasingly important issue for modern integrated circuits. Thinner gate oxides, complex chips with multiple power supplies and/or mixed-signal blocks, larger chip capaci-tance and faster circuit operation all contribute to increased ESD-sensitivity of advanced semiconductor products [1]. Detailed understanding of complex circuit-device interac-tions is essential for the design of effective ESD protection. This paper presents results of an ESD failure analysis, where excessive distance between the IO pad and the power supply ESD protection can lead to permanent failure during ESD stress. The critical distance for a given protection type is calculated and remedies for the situation shown. Industrial ESD Analysi