A Fast, Accurate and Reliable Estimation for Rapid Design Space Exploration of Superscalar Architecture

simulation This paper proposes a very accurate and relatively fast method of estimating cycle-counts of target applications to rapidly find architecture parameters of superscalar processors that satisfy user-provided real-time constraints. Furthermore, by giving a tight upper bound on the estimation error, user can convince himself of the estimation result. The method is based on a classification of benchmark characteristics into two pieces: architecture independent and architecture dependent ones. The speedup comes from the fact that we need only one full-simulation to obtain the architecture independent information instead of conducting simulation whenever parameters change. Moreover, we can reduce the simulation time in obtaining architecture-dependent ones through sampled-data simulation with a little loss of accuracy. Experimental results show 86 times of speedup against full data simulation with 0.8 % estimation error on average, if the desired error bound is set to 5%. When we set desired error bound to 20%, speedup increases to 134 with 2.8 % estimation error on average