A performance comparison of DRAM memory system optimizations for SMT processors

Memory system optimizations have been well studied on single-threaded systems; however, the wide use of si-multaneous multithreading (SMT) techniques raises ques-tions over their effectiveness in the new context. In this study, we thoroughly evaluate contemporary multi-channel DDR SDRAM and Rambus DRAM systems in SMT systems, and search for new thread-aware DRAM optimization tech-niques. Our major ndings are: (1) in general, increas-ing the number of threads tends to increase the memory concurrency and thus the pressure on DRAM systems, but some exceptions do exist; (2) the application performance is sensitive to memory channel organizations, e.g. indepen-dent channels may outperform ganged organizations by up to 90%; (3) the DRAM latency reduction through improv-ing row buffer hit rates becomes less effective due to the in-creased bank contentions; and (4) thread-aware DRAM ac-cess scheduling schemes may improve performance by up to 30 % on workload mixes of memory-intensive applications. In short, the use of SMT techniques has somewhat changed the context of DRAM optimizations but does not make them obsolete.