We present a novel approach to parallelizing a lexical-tree based LVCSR decoding algorithm for multi-core desktop processors. The approach distributes the search space among the cores by dividing the lexical tree in a way that mini-mizes communication between cores. Synchronization and load balancing schemes for this approach are described. The parallel algorithm is benchmarked on a 5k-word Wall Street Journal task. The context-dependent triphone model baseline system achieves a WER of 8.4%. The algorithm is shown to achieve a speedup of 1.63 on an Intel Core 2 Duo processor, with an average CPU utilization of 86%. The results also show that increasing the width of pruning schemes improves the parallel speedup. 1
Abstract — The paper presents the novel design of a one-pass large vocabulary continuous-speech reco...
This paper describes the evaluation of the !V$N$>$_!W stack decoder for LVCSR on a 5000 word Jap...
In this paper, we propose a hybrid parallel decoding strategy for HEVC which combines task-level par...
Publication in the conference proceedings of EUSIPCO, Lausanne, Switzerland, 200
Increasingly, physical limitations lead to a shift from high clocked single core processors to CPUs ...
State-of-the-art speech-recognition systems can successfully perform simple tasks in real-time on mo...
To communicate with a computer in spoken language is an unattained challenge of Artificial Intellige...
Parallel scalability allows an application to efficiently uti-lize an increasing number of processin...
The multi-core machines open new doors to achieve parallelism in single machine. This new architectu...
The advent of multi-core architecture has highly influenced the area of high performance computing. ...
Purpose: Massive multi-core architecture is rapidly becoming the standard in digital technology due ...
We present a parallel approach for integrating speech and natural language understanding. The method...
International audienceParallel turbo decoding is becoming mandatory in order to achieve high through...
We present a parallel approach for integrating speech and natural language understanding. The method...
For years researchers have worked toward finding a way to allow people to talk to machines in the sa...
Abstract — The paper presents the novel design of a one-pass large vocabulary continuous-speech reco...
This paper describes the evaluation of the !V$N$>$_!W stack decoder for LVCSR on a 5000 word Jap...
In this paper, we propose a hybrid parallel decoding strategy for HEVC which combines task-level par...
Publication in the conference proceedings of EUSIPCO, Lausanne, Switzerland, 200
Increasingly, physical limitations lead to a shift from high clocked single core processors to CPUs ...
State-of-the-art speech-recognition systems can successfully perform simple tasks in real-time on mo...
To communicate with a computer in spoken language is an unattained challenge of Artificial Intellige...
Parallel scalability allows an application to efficiently uti-lize an increasing number of processin...
The multi-core machines open new doors to achieve parallelism in single machine. This new architectu...
The advent of multi-core architecture has highly influenced the area of high performance computing. ...
Purpose: Massive multi-core architecture is rapidly becoming the standard in digital technology due ...
We present a parallel approach for integrating speech and natural language understanding. The method...
International audienceParallel turbo decoding is becoming mandatory in order to achieve high through...
We present a parallel approach for integrating speech and natural language understanding. The method...
For years researchers have worked toward finding a way to allow people to talk to machines in the sa...
Abstract — The paper presents the novel design of a one-pass large vocabulary continuous-speech reco...
This paper describes the evaluation of the !V$N$>$_!W stack decoder for LVCSR on a 5000 word Jap...
In this paper, we propose a hybrid parallel decoding strategy for HEVC which combines task-level par...