Parasitic Effects Reduction for Wafer-Level Packaging Of RF-MEMS

In RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The package concept used is based on a wafer-level bonding of a capping silicon substrate with through-substrate interconnect to an RF-MEMS wafer. The capping silicon substrate resistivity, substrate thickness and the geometry of through-substrate electrical interconnect vias have been optimized using finite-element electromagnetic simulations (Ansoft HFSS). Moreover, a preliminary analysis on the electromagnetic effects of the capping wafer bonding techniques (solder bump reflow and isotropic or anisotropic conductive adhesive [1]) is presented