Systolic Super Summation with Reduced Hardware

A principal limitation in accuracy for scientific computation performed with floating-point arithmetic may be traced to the computation of repeated sums, such as those which arise in inner products. As previously reported, a systolic super summer is a cellular piece of hardware for the summation of floating-point numbers. The appara-tus receives floating-point summands, converting them into a fixed-point form within a sieve-like cellular array. The emerging fixed-point numbers then are summed in a pipelined array of long accumulators. An improved design is presented for systolic su-per summation’s sieve. Although the new sieve is structurally simpler and uses less hardware, the throughput per unit area is the same as the previously designed sieve. The architectural regularity of the new sieve makes it ideal for implementation in VLSI circuit technology.