We describe the condition that a sequential digital design is a safe replacement for an existing design without making any as-sumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced by a new design, the interacting environment cannot detect the change by observ-ing the input-output behavior of the new design; conversely, if a replacement design does not satisfy our condition an environment can potentially detect the replacement (in this sense the replace-ment is potentially unsafe). Our condition allows simplification of the state transition diagram of an original design. We use the safe replacement condition to derive a s...
Given a system design (SD), a key task is to optimize this design to reduce the probability of catas...
In order to reduce the test development cost and guarantee testable designs, it is essential to have...
All electronic processing components in future deep nanotechnologies will exhibit high noise level a...
This paper presents a testable synthesis methodology applicable to any top-down design method based ...
Most problems in logic synthesis are computationally hard, and are solved using heuristics. This oft...
Recent work has identified the notion of safe replacement for se-quential synchronous designs that m...
We propose an algorithm for area optimisation of sequential circuits through redundancy removal. The...
Retiming combined with combinational optimization is a power-ful sequential synthesis method. Howeve...
Full sequential equivalence checking by state space traversal has been shown to be unpractical for l...
This proposal describes a comprehensive methodology for performance-oriented synthesis of multi-leve...
This paper investigates the impact of non-determinism and modularity on the complexity of incrementa...
International audienceWe propose a technique for the synthesis of safety controllers for switched sy...
128 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.We address the issue of trans...
International audienceThis paper deals with the synthesis of state-feedback controllers using approx...
All electronic processing components in future deep nanotechnologies will exhibit high noise level a...
Given a system design (SD), a key task is to optimize this design to reduce the probability of catas...
In order to reduce the test development cost and guarantee testable designs, it is essential to have...
All electronic processing components in future deep nanotechnologies will exhibit high noise level a...
This paper presents a testable synthesis methodology applicable to any top-down design method based ...
Most problems in logic synthesis are computationally hard, and are solved using heuristics. This oft...
Recent work has identified the notion of safe replacement for se-quential synchronous designs that m...
We propose an algorithm for area optimisation of sequential circuits through redundancy removal. The...
Retiming combined with combinational optimization is a power-ful sequential synthesis method. Howeve...
Full sequential equivalence checking by state space traversal has been shown to be unpractical for l...
This proposal describes a comprehensive methodology for performance-oriented synthesis of multi-leve...
This paper investigates the impact of non-determinism and modularity on the complexity of incrementa...
International audienceWe propose a technique for the synthesis of safety controllers for switched sy...
128 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.We address the issue of trans...
International audienceThis paper deals with the synthesis of state-feedback controllers using approx...
All electronic processing components in future deep nanotechnologies will exhibit high noise level a...
Given a system design (SD), a key task is to optimize this design to reduce the probability of catas...
In order to reduce the test development cost and guarantee testable designs, it is essential to have...
All electronic processing components in future deep nanotechnologies will exhibit high noise level a...