A Versatile Directory Scheme ( DirzNB+L) and Its Implementation on BY91-1 Multiprocessors System

Cache coherence and synchronization between processors have been two critical issues in designing a shared memory multiprocessors system. From the perspective of hardware design, a directory based cache coherence protocol and lock mechanism are employed to prevent inconsistency of caches and warrant atomic memory accesses. The BY91-1 multiprocessors ejiciently integrate supports for cache coherence and hardware based primitives by using a uniform directory scheme which is dubbed as DirzNB+L. Thts integration allowsfor low hardware overhead while maintaining both a coherent caches system and indivisible memory accesses in,,a scalable and cohesive fashion. This paper describes the design and rationale of this versatile directory scheme. Results on the evaluation of dtflerent directory schemes based on a preliminary simulator-CASIMU demonstrate that Dir,NB+L scheme is cost-eflective. We also report on the experience gained by implementing this directory scheme on BY91-1 multiprocessors system. We believe that this scheme is well suitedfor CC-NL.444 architecture. 1