Development of a Radiation Tolerant 2.0 V Standard Cell Library using a Commercial Deep Submicron CMOS Technology for the LHC

A standard cell library was developed using a commercial 0.24 µm, 2.5 V CMOS technology. Radiation tolerant design techniques have been employed on the layout of the cells to achieve the total dose hardness levels required by LHC experiments. The library consists of digital core cell elements as well as a number of I/O pad cells. Additionally, it includes a pair of differential driver and receiver pads implementing the LVDS standard. The library cells have been fully characterised and the necessary descriptions to facilitate simulation have also been generated. The presented library features 5 times increase in speed accompanied by 26 times reduction in power consumption as well as an increase of 8 times in gate densities when compared to a currently available 0.8 µm CMOS technology. To prove the concept and to evaluate the radiation tolerance of the cells, a few demonstration circuits were implemented. The results of the radiation hardness tests are being reported. 1