Résumé. 2014 Un procédé de gravure sèche a été mis au point pour la fabrication de transistors MOS submicro-niques en technologie canal N grille silicium. La gravure ionique réactive a été utilisée pour graver le Si3N4, le silicium polycristallin et le SiO2 déposé dopé au phosphore (PSG). L’aluminium a été gravé par plasma. Le pro-cédé foumit une gravure en pente des trous de contact dans le PSG et une surface aplanie du PSG, ceci pour amé-liorer la couverture aux marches de la métallisation et pour faciliter la gravure de l’aluminium. Des transistors MOS ayant des longueurs de grilles de 0,6 03BCm ont été fabriqués avec succès selon ce procédé. Abstract. 2014 An anisotropic dry etching process for submicrometer silicon gate N channel MOS t...
Dry etching has been used in conjunction with masked ion beam lithography to fabricate devices with ...
Les gravures par plasma pour les technologies sub 14nm nécessitent de bien contrôler la gravure de c...
In the context of transistor size miniaturization the motivation of this work was focused on the fab...
An anisotropic dry etching process for submicrometer silicon gate N channel MOS technology has been ...
L’étape de gravure des espaceurs de grille est de plus en plus exigeante avec la réduction de la lon...
Les réductions des dimensions des dispositifs CMOS imposent d’introduire de nouvelles architectures ...
This paper demonstrates a low damage inductively coupled plasma SF6/C4F8 dry etch process for the re...
This paper presents a low damage inductively coupled plasma (ICP) etching process to define sub-100 ...
This Thesis describes the application of high resolution electron beam lithography and dry etching t...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
Abstract—Damage-free sputter deposition and highly selec-tive dry-etch processes have been developed...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
Phase Shift Masks (PSMs) allow to extend the optical lithography to the deep submicrometer range. A ...
In this investigation, efforts have been made to move the Microelectronic Engineering Program at Roc...
MOSFET (metal-oxide-semiconductor field effect transistor) is one of the variations of the MOS trans...
Dry etching has been used in conjunction with masked ion beam lithography to fabricate devices with ...
Les gravures par plasma pour les technologies sub 14nm nécessitent de bien contrôler la gravure de c...
In the context of transistor size miniaturization the motivation of this work was focused on the fab...
An anisotropic dry etching process for submicrometer silicon gate N channel MOS technology has been ...
L’étape de gravure des espaceurs de grille est de plus en plus exigeante avec la réduction de la lon...
Les réductions des dimensions des dispositifs CMOS imposent d’introduire de nouvelles architectures ...
This paper demonstrates a low damage inductively coupled plasma SF6/C4F8 dry etch process for the re...
This paper presents a low damage inductively coupled plasma (ICP) etching process to define sub-100 ...
This Thesis describes the application of high resolution electron beam lithography and dry etching t...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
Abstract—Damage-free sputter deposition and highly selec-tive dry-etch processes have been developed...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
Phase Shift Masks (PSMs) allow to extend the optical lithography to the deep submicrometer range. A ...
In this investigation, efforts have been made to move the Microelectronic Engineering Program at Roc...
MOSFET (metal-oxide-semiconductor field effect transistor) is one of the variations of the MOS trans...
Dry etching has been used in conjunction with masked ion beam lithography to fabricate devices with ...
Les gravures par plasma pour les technologies sub 14nm nécessitent de bien contrôler la gravure de c...
In the context of transistor size miniaturization the motivation of this work was focused on the fab...