Retargetable static timing analysis for embedded software

unified machine description language. We address the second one by modeling the effects of several, hitherto largely ignored, important features in modem processors. This paper presents a novel approach for retargetable static software timing analysis. Specifically, we target the problem of determining bourids on the execution time of a program on modem processors, and solve this problem in a retargetable software development environment. Another contribution of this paper is the modeling of important features in contemporary architectures, such as branch prediction, predication, and interrupts. To be suitable for static timing analysis, the program must be statically predictable, e.g. it cannot have infinite loops or dynamic function calls. In general, the analysis is performed at task-level, in which we do not consider the effects of preemption or instruction pre-fetching, which have great impact on system performance, and have been rarely handled thus far. These ideas allow to. build a timing analysis tool that is efficient, accurate, modular and retargetable. We present preliminary results for sample embedded programs to demonstrate the applicability of the proposed approach. 1