Current interconnect standards providing hardware sup-port for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implemen-tations do not offer so many VCs because they increase the complexity of the switch and the scheduling delays. We have shown that this number of VCs can be significantly reduced, because it is enough to use two VCs for QoS purposes at each switch port. In this paper, we cover the weaknesses of that proposal and, not only we reduce VCs, but we also improve performance due to the flexibility assigning buffer memory.
Over the last several years, a variety of multipoint virtual circuit switching systems have been pro...
International audienceVirtual switches are a key elements within the new paradigms of Software Defin...
We simulate an ATM VPI-switch with pipelined (or shared-slot data buffer) and output buffering. Our ...
Current interconnect standards providing hardware support for quality of service (QoS) consider up t...
Abstract—Both QoS support and congestion management techniques become essential to achieve good netw...
Abstract. Both QoS support and congestion management techniques have become essential for achieving ...
Using buffered crossbar as a core switch fabric, we build a combined input-crosspoint-output queued ...
Recent development on Ethernet switching to provide Single Root I/O Virtualization (SR-IOV) on netwo...
An ATM quality of service (QoS) controller which combines perconnection buffer management with a tab...
Memory used in high-speed switching often needs to be customer designed and is expensive. As the lin...
Virtual channels are an appealing flow control technique for on-chip interconnection networks (NoCs)...
Abstract—Large systems-on-chip (SoCs) and chip multiprocessors (CMPs), incorporating tens to hundred...
Abstract-The server virtualization architecture encompassing sharing of storage subsystems among vir...
This work considers contention resolution in optical packet switches and proposes a switch architec...
Summarization: One of the most widely used architectures for packet switches is the crossbar. A spec...
Over the last several years, a variety of multipoint virtual circuit switching systems have been pro...
International audienceVirtual switches are a key elements within the new paradigms of Software Defin...
We simulate an ATM VPI-switch with pipelined (or shared-slot data buffer) and output buffering. Our ...
Current interconnect standards providing hardware support for quality of service (QoS) consider up t...
Abstract—Both QoS support and congestion management techniques become essential to achieve good netw...
Abstract. Both QoS support and congestion management techniques have become essential for achieving ...
Using buffered crossbar as a core switch fabric, we build a combined input-crosspoint-output queued ...
Recent development on Ethernet switching to provide Single Root I/O Virtualization (SR-IOV) on netwo...
An ATM quality of service (QoS) controller which combines perconnection buffer management with a tab...
Memory used in high-speed switching often needs to be customer designed and is expensive. As the lin...
Virtual channels are an appealing flow control technique for on-chip interconnection networks (NoCs)...
Abstract—Large systems-on-chip (SoCs) and chip multiprocessors (CMPs), incorporating tens to hundred...
Abstract-The server virtualization architecture encompassing sharing of storage subsystems among vir...
This work considers contention resolution in optical packet switches and proposes a switch architec...
Summarization: One of the most widely used architectures for packet switches is the crossbar. A spec...
Over the last several years, a variety of multipoint virtual circuit switching systems have been pro...
International audienceVirtual switches are a key elements within the new paradigms of Software Defin...
We simulate an ATM VPI-switch with pipelined (or shared-slot data buffer) and output buffering. Our ...