Power Estimation for Sequential Logic Circuits

Abstract — We describe an approach to estimate the average power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the esti-mation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and pro-grams can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estima-tion can be carried out using existing sequential circuit power estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit. I