Add to ORKGAbstract: A failure shape analysis system is developed to quickly analyze the defect distribution of memories. Compared to the original system, the newer one consists of several programs feasible both on workstations and PCs. These programs transform and grasp the required data for further failure analysis. The complete system is highly reliable and fault tolerant for the entire manufacture and test procedure. It can achieve the similar defect distribution as the original one but with only 11 % and 6 % of run time on workstations and PCs, respectively
The research focuses on conducting failure analysis and reliability study to understand and analyze ...
The application of a combined test-error-correcting procedure is studied to improve the mean time to...
This paper presents a new approach to configure compressed bit fail maps to allow fail pattern recog...
[[abstract]]As VLSI technology advances and memories occupy more and more area in a typical SOC, mem...
[[abstract]]A memory failure analysis framework is developed-the Failure Analyzer for MEmories (FAME...
[[abstract]]Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (...
[[abstract]]We present an error catch and analysis (ECA) system for semiconductor memories. The syst...
A Memory Debug Technique plays a key role in System-on-chip (SOC) product development and yield ramp...
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2012In moder...
We propose a methodology for systematically injecting defects into an SRAM and simulating the effect...
Repairable embedded memories help improve the overall yield of an IC. We have developed a yield anal...
NUMBER OF PAGES: xv+413Considers failures disrupting the programs in microprocessors, i.e. failures ...
This paper focuses on fully automated analysis of failure event data in the concept and early develo...
Abstract: Due to the large die size and the complex fabrication process for combining memories and ...
Traditional reliability-related models for fault-tolerant systems are used to predict system reliabi...
The research focuses on conducting failure analysis and reliability study to understand and analyze ...
The application of a combined test-error-correcting procedure is studied to improve the mean time to...
This paper presents a new approach to configure compressed bit fail maps to allow fail pattern recog...
[[abstract]]As VLSI technology advances and memories occupy more and more area in a typical SOC, mem...
[[abstract]]A memory failure analysis framework is developed-the Failure Analyzer for MEmories (FAME...
[[abstract]]Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (...
[[abstract]]We present an error catch and analysis (ECA) system for semiconductor memories. The syst...
A Memory Debug Technique plays a key role in System-on-chip (SOC) product development and yield ramp...
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2012In moder...
We propose a methodology for systematically injecting defects into an SRAM and simulating the effect...
Repairable embedded memories help improve the overall yield of an IC. We have developed a yield anal...
NUMBER OF PAGES: xv+413Considers failures disrupting the programs in microprocessors, i.e. failures ...
This paper focuses on fully automated analysis of failure event data in the concept and early develo...
Abstract: Due to the large die size and the complex fabrication process for combining memories and ...
Traditional reliability-related models for fault-tolerant systems are used to predict system reliabi...
The research focuses on conducting failure analysis and reliability study to understand and analyze ...
The application of a combined test-error-correcting procedure is studied to improve the mean time to...
This paper presents a new approach to configure compressed bit fail maps to allow fail pattern recog...