Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis

Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded con-trollers [ErHeBe93]. Target system of COSYMA is a core processor with application specific co–processors. The system speedup for standard programs compared to a sin-gle 33MHz RISC processor solution with fast, single cy-cle access RAM was typically less than 2 due to restric-tions in high-level co–processor synthesis, and incorrectly estimated back end tool performance, such as hardware synthesis, compiler optimization and communication opti-mization. Meanwhile, a high-level synthesis tool for high-performance co–processors in co-synthesis has been devel-oped. This paper explains the requirements and the main features of the high-level synthesis system and its integra