Add to ORKGThis paper presents a two-step, RC-interconnect in-sensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to charac-terize a driver with the LTV model and how to apply that model in static timing analysis. With the LTV model, the delay error caused by the driver’s nonlinearity is reduced significantly because the driver’s linear- and saturation-region operations are characterized individually. Because both the linear- and saturation-region models are insen-sitive to interconnect loads, it is sufficient to use a small number of LTV models for a wide range of possible inter-connect loads. Due to the same reason, the LTV model is robust, does not require iterations, and makes timing analysis fast. This ...
Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of ...
This thesis presents systematic modeling and analysis techniques for the accurate and efficient timi...
In this paper, models of the input admittance of RC interconnects are discussed in depth to understa...
Abstract: For improved efficiency, static timing analyzers represent the interconnect driving point ...
125 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.The methodologies and techniq...
Static timing analysis (STA) is a key step in the physical design optimization of VLSI designs. The ...
A compact model for RLC interconnect lines, in the form of a twopath hybrid ladder, is proposed for ...
This work presents a methodology for creating efficient yet accurate timing macromodels which are te...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (...
We study signal integrity effects on statistical timing analysis, e.g., interconnect and gate delay ...
textIn this dissertation we present two techniques with applications in the area of signal propagat...
textIn this dissertation we present two techniques with applications in the area of signal propagat...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Static timing analysis has traditionally used the PERT method for identifying the critical path of a...
Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of ...
This thesis presents systematic modeling and analysis techniques for the accurate and efficient timi...
In this paper, models of the input admittance of RC interconnects are discussed in depth to understa...
Abstract: For improved efficiency, static timing analyzers represent the interconnect driving point ...
125 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.The methodologies and techniq...
Static timing analysis (STA) is a key step in the physical design optimization of VLSI designs. The ...
A compact model for RLC interconnect lines, in the form of a twopath hybrid ladder, is proposed for ...
This work presents a methodology for creating efficient yet accurate timing macromodels which are te...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (...
We study signal integrity effects on statistical timing analysis, e.g., interconnect and gate delay ...
textIn this dissertation we present two techniques with applications in the area of signal propagat...
textIn this dissertation we present two techniques with applications in the area of signal propagat...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Static timing analysis has traditionally used the PERT method for identifying the critical path of a...
Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of ...
This thesis presents systematic modeling and analysis techniques for the accurate and efficient timi...
In this paper, models of the input admittance of RC interconnects are discussed in depth to understa...