This paper proposes a simulation-based soft error esti-mation methodology for computer systems. Accumulating soft error rates (SERs) of all memories in a computer sys-tem results in pessimistic soft error estimation. This is be-cause memory cells are used spatially and temporally and not all soft errors in them make the computer system faulty. Our soft-error estimation methodology considers the loca-tions and the timings of soft errors occurring at every level of memory hierarchy and estimates the soft errors of the whole system using instruction-set simulation. Our experi-ment demonstrates that the reliability of computer systems depends on not only SERs of memories but also the behavior of software running on the systems
System reliability has become a key design aspect for computer systems due to the aggressive technol...
This paper presents an empirical investigation on the soft error sensitivity (SES) of microprocessor...
International audienceStatic raw soft-error rates (SER) of COTS microprocessors are classically obta...
This paper proposes a simulation-based soft error esti-mation methodology for computer systems. Accu...
SUMMARY This paper proposes a soft-error model for accurately esti-mating reliability of a computer ...
The topic of this thesis is about soft-errors in digital systems. Different aspects of soft-errors h...
International audienceThis paper presents a new methodology for the simulation of soft errors in dig...
Soft errors are a growing concern for processor reliability. Recent work has motivated architecture ...
In this paper a simulator of soft errors (SEUs) in the configuration memory of SRAM-based FPGAs is p...
System reliability has become a key design aspect for computer systems due to the aggressive technol...
Soft errors due to cosmic rays cause reliability problems during lifetime operation of digital syste...
International audienceThis paper presents two error models to evaluate safety of a software error de...
In this paper a simulator of soft errors (SEUs) in the configuration memory of SRAM-based FPGAs is p...
This paper proposes the use of metrics to refine system design for soft errors protection in system ...
Minimizing the risk of system failure in any computer structure requires identifying those component...
System reliability has become a key design aspect for computer systems due to the aggressive technol...
This paper presents an empirical investigation on the soft error sensitivity (SES) of microprocessor...
International audienceStatic raw soft-error rates (SER) of COTS microprocessors are classically obta...
This paper proposes a simulation-based soft error esti-mation methodology for computer systems. Accu...
SUMMARY This paper proposes a soft-error model for accurately esti-mating reliability of a computer ...
The topic of this thesis is about soft-errors in digital systems. Different aspects of soft-errors h...
International audienceThis paper presents a new methodology for the simulation of soft errors in dig...
Soft errors are a growing concern for processor reliability. Recent work has motivated architecture ...
In this paper a simulator of soft errors (SEUs) in the configuration memory of SRAM-based FPGAs is p...
System reliability has become a key design aspect for computer systems due to the aggressive technol...
Soft errors due to cosmic rays cause reliability problems during lifetime operation of digital syste...
International audienceThis paper presents two error models to evaluate safety of a software error de...
In this paper a simulator of soft errors (SEUs) in the configuration memory of SRAM-based FPGAs is p...
This paper proposes the use of metrics to refine system design for soft errors protection in system ...
Minimizing the risk of system failure in any computer structure requires identifying those component...
System reliability has become a key design aspect for computer systems due to the aggressive technol...
This paper presents an empirical investigation on the soft error sensitivity (SES) of microprocessor...
International audienceStatic raw soft-error rates (SER) of COTS microprocessors are classically obta...