Overview of Oversampling Clock and Data Recovery Circuits

Phase-Locked Loop (PLL) based Clock and Data Recovery (CDR) circuits use a 2x-oversampling (2XO) of the incoming Non-Return to Zero (NRZ) data stream to recover the data. As an extension of the idea, 3x-oversampling (3XO) CDR circuits provide improved performance in the presence of total asym-metric jitter. This paper presents an overview of the oversam-pling CDR circuits with an emphasis on digital architectures. These include, but are not limited to, the 3XO jitter-tolerant variable-interval 3XO architecture, the 3XO eye-tracking archi-tecture, and the blind oversampling architecture. We propose a modified architecture that utilizes multiple rotating phases to improve the performance of the 3XO eye-tracking architecture