application analysis, superscalar architecture The understanding of instruction set usage in typical DOS/Windows applications plays a very important role in designing high performance x86 compatible microprocessors. This paper presents the tools to such analysis, the analysis results, and their implications on the design of a superscalar processor, based on a RISC core, for efficient x86 instruction execution. The analysis tools include monitoring systems for both DOS and Windows 95 applications, either with or without source code. Many commercial software programs are analyzed, including MS Word, MS Excel, Netscape, Netterm, DOS commands, etc. The analyzed results reported in this paper include execution frequencies of x86 instructions, th...
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectiv...
Includes bibliographical references (pages 92)Intel 8086 is the advanced, high-performance, 16-blt\u...
In out-of-order issue superscalar microprocessors, instructions must be buffered before they are iss...
There is a huge variety of processor microarchitectural techniques to decrease the program execution...
???? x86?????????????????? In this work, we first analyzed the features of x86 instruction set and d...
This dissertation analyzes x86 processor models in order to better understand the impact that the x8...
Workload characterization has been proven an essential tool to architecture design and performance e...
Abstract: This paper treats the problem of detection of data hazards in superscalar execution. The a...
Real-time aspects are becoming more important in standard desktop PC environments and x86 based proc...
A new approach for power analysis of microprocessors has recently been proposed [14]. The idea is to...
A new approach for power analysis of microprocessors has recently been proposed [1]. The idea is to ...
We present a simple technique for instruction-level parallelism and analyze its performance impact. ...
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectiv...
The main aim of this short paper is to investigate multiple-instruction-issue in a high-performance ...
A new approach for power analysis of microprocessors has recently been proposed [14]. The idea is to...
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectiv...
Includes bibliographical references (pages 92)Intel 8086 is the advanced, high-performance, 16-blt\u...
In out-of-order issue superscalar microprocessors, instructions must be buffered before they are iss...
There is a huge variety of processor microarchitectural techniques to decrease the program execution...
???? x86?????????????????? In this work, we first analyzed the features of x86 instruction set and d...
This dissertation analyzes x86 processor models in order to better understand the impact that the x8...
Workload characterization has been proven an essential tool to architecture design and performance e...
Abstract: This paper treats the problem of detection of data hazards in superscalar execution. The a...
Real-time aspects are becoming more important in standard desktop PC environments and x86 based proc...
A new approach for power analysis of microprocessors has recently been proposed [14]. The idea is to...
A new approach for power analysis of microprocessors has recently been proposed [1]. The idea is to ...
We present a simple technique for instruction-level parallelism and analyze its performance impact. ...
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectiv...
The main aim of this short paper is to investigate multiple-instruction-issue in a high-performance ...
A new approach for power analysis of microprocessors has recently been proposed [14]. The idea is to...
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectiv...
Includes bibliographical references (pages 92)Intel 8086 is the advanced, high-performance, 16-blt\u...
In out-of-order issue superscalar microprocessors, instructions must be buffered before they are iss...