Current multicore architectures offer high throughput by increasing hardware resource utilization. As the number of cores in a multi-core system increases, providing Quality of Service (QoS) to appli-cations in addition to throughput is becoming an important prob-lem. In this work, we present FlexDCP, a framework that allows the Operating System (OS) to guarantee a QoS for each applica-tion running in a chip multiprocessor. FlexDCP directly estimates the performance of applications for different cache configurations instead of using indirect measures of performance like the num-ber of misses. This information allows the OS to convert QoS re-quirements into resource assignments. Consequently, it offers more flexibility to the OS as it can op...
[EN] Shared caches have become the common design choice in the vast majority of modern multi-core an...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Abstract—In order to increase utilization, multicore pro-cessors share memory resources among an inc...
As we enter the era of CMP platforms with multiple threads/cores on the die, the diversity of the si...
Cache hierarchies have been traditionally designed for usage by a single application, thread or core...
The evolution of microprocessor design in the last few decades has changed significantly, moving fro...
Efficiently allocating shared on-chip resources across cores is critical to optimize execution in ch...
Multicore processors are ubiquitous in servers and have started dominating other domains, such as em...
This paper presents a detailed study of fairness in cache sharing between threads in a chip multipro...
Chip Multi-Processor (CMP) platforms, well-established in the server, desktop and embedded domain, s...
The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted lev...
Designing chip multiprocessors (CMPs) that scale to more than a handful of cores is an important goa...
Chip multiprocessors have the potential to exploit thread level parallelism, particularly attractive...
\ua9 2019 IEEE Applications that are run on multicore systems without performance targets can waste ...
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads c...
[EN] Shared caches have become the common design choice in the vast majority of modern multi-core an...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Abstract—In order to increase utilization, multicore pro-cessors share memory resources among an inc...
As we enter the era of CMP platforms with multiple threads/cores on the die, the diversity of the si...
Cache hierarchies have been traditionally designed for usage by a single application, thread or core...
The evolution of microprocessor design in the last few decades has changed significantly, moving fro...
Efficiently allocating shared on-chip resources across cores is critical to optimize execution in ch...
Multicore processors are ubiquitous in servers and have started dominating other domains, such as em...
This paper presents a detailed study of fairness in cache sharing between threads in a chip multipro...
Chip Multi-Processor (CMP) platforms, well-established in the server, desktop and embedded domain, s...
The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted lev...
Designing chip multiprocessors (CMPs) that scale to more than a handful of cores is an important goa...
Chip multiprocessors have the potential to exploit thread level parallelism, particularly attractive...
\ua9 2019 IEEE Applications that are run on multicore systems without performance targets can waste ...
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads c...
[EN] Shared caches have become the common design choice in the vast majority of modern multi-core an...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Abstract—In order to increase utilization, multicore pro-cessors share memory resources among an inc...