The performance of base DLS mechanism inOn

Both issue-queue phases (wakeup and select) con-stitute a hardware loop, the scheduling loop, because an instruction must be selected before waking its dependents instructions up. This hardware loop is critical because its latency must be only one cycle in order to execute dependent instructions in consecu-tive cycles (back-to-back). Issue-queue timing directly depends on of instructions woken up in advance will not compete for selection until all producer-level instructions have been selected for execution. As DLS mechanism is not speculative, both false selections [23] and pileup victims [3] are avoided. Moreover DLS mechanism requires only a Wakeup Matrix as [3] in contrast with [9] and [23] which require two