A Low-Voltage Compatible Two-Stage Amplifier with ≥120dB Gain in Standard Digital CMOS

A low-voltage compatible 120dB gain two-stage amplifier in standard digital CMOS with 3 transistors between VDD and VSS is presented and circuit details are discussed. With the use of precision voltage attenuator, output level monitoring circuits (OLMC) and a digital tuning network, the first stage was tested, achieving ≥76dB DC gains over 2Vpp output swing. With a modest-gain 2nd stage, ≥120dB (by simulation, or 110 dB based on test) gain can be achieved over 2Vpp swing with PM ≥ 56o at GBW≥120 MHz when VDD=3.5V without OLMC