Design Tool and Methodologies for InterconnectReliability Analysis in Integrated CircuitsbySyed Mohiul AlamS.M., Massachusetts Institute of Technology, 2001B.S., The University of Texas at Austin, 1999Submitted to theDepartment of Electrical Engineering and Computer Sciencein partial fulfillment of the requirements for the degree ofDoctor of Philosophy in Electrical Engineering and Computer Scienceat theMASSACHUSETTS INSTITUTE OF TECHNOLOGYSeptember 2004c© 2004 Massachusetts Institute of TechnologyAll Rights ReservedAuthor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Department of Electrical Engineering and Computer ScienceAugust 31, 2004Certified by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Donald E. TroxelProfessor of Electrical Engineering and Computer ScienceThesis SupervisorCertified by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Carl V. ThompsonStavros Salapatas Professor of Materials Science and EngineeringThesis SupervisorRead by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Duane S. BoningAssociate Department Head and Professor of Electrical Engineeringand Computer ScienceThesis ReaderAccepted by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Arthur C. SmithChairman, Department Committee on Graduate Students2Design Tool and Methodologies for Interconnect ReliabilityAnalysis in Integrated CircuitsbySyed Mohiul AlamSubmitted to the Department of Electrical Engineering and Computer Scienceon August 31, 2004, in partial fulfillment of therequirements for the degree ofDoctor of Philosophy in Electrical Engineering and Computer ScienceAbstractTotal on-chip interconnect length has been increasing exponentially with technologyscaling. Consequently, interconnect-driven design is an emerging trend in state-of-the-art integrated circuits. Cu-based interconnect technology is expected to meetsome of the challenges of technology scaling. However, Cu interconnects still pose areliability concern due to electromigration-induced failure over time.The major contribution of this thesis is a new reliability CAD tool, SysRel, forthermal-aware reliability analysis with either Al or Cu metallization technology inconventional and three-dimensional integrated circuits. An interconnect tree is thefundamental reliability unit for circuit-level reliability assessments for metallizationschemes with fully-blocking boundaries at the vias. When vias do not block electro-migration as indicated in some Cu experimental studies, multiple trees linked by anon-blocking via are merged to create a single fundamental reliability unit. SysRelutilizes a tree-based hierarchical analysis that sufficiently captures the differences be-tween electromigration behavior in Al and Cu metallizations. The hierarchical flowfirst identifies electromigration-critical nets or “mortal” trees, applies a default modelto estimate the lifetimes of individual trees, and then produces a set of full-chip reli-ability metrics based on stochastic analysis using the desired lifetime of the circuit.We have exercised SysRel to compare layout-specific reliability with Cu and Almetallizations in various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. Therequired improvement will increase as low-k dielectric materials are introduced andliner thicknesses are reduced in future.Thesis Supervisor: Donald E. TroxelTitle: Professor of Electrical Engineering and Computer ScienceThesis Supervisor: Carl V. ThompsonTitle: Stavros Salapatas Professor of Materials Science and Engineering34DedicationTo my motherShahana Alam56AcknowledgmentsI am grateful to my co-advisors Professors Donald E. Troxel and Carl V. Thompsonfor their guidance and support throughout the years at MIT. There were numerousdiscussions and meetings leading to the successful completion of this thesis. I wouldlike to thank Professor Duane S. Boning for serving in my thesis committee. Heprovided valuable feedback during one-on-one and committee meetings.This research was supported by Microelectronics Advanced Research Corporation(MARCO) Interconnect Focus Research Center Program. I got numerous opportuni-ties to actively participate in annual and quarterly reviews and to interact with otherresearchers and industry members in the program. I acknowledge the valuable inter-actions with Professor James Meindl, Professor Kenneth Goodson, Professor AnanthaChandrakasan, Professor Rafael Reif, Sungjun Im, Jae-Mo Koo, Eric Pop, and TyroneHill.I would like to thank my colleagues at MIT, Frank Wei, Zung-Sun Choi, Ramku-mar Krishnan, Rajappa Tadepalli, and Andrew Takahashi, for their support throughdiscussions and collaboration. This research is partially built upon prior work in ourgroup. The Magic layout parsing and data storage in SysRel are based on YonaldCherry’s earlier work with ERNI. Electromigration analysis in Cu metallization isbased on experimental and modelling work by Gan Chee Lip, Frank Wei, and Zung-Sun Choi. Stefan Hau-Riege developed the concept of hierarchical reliability analysiswith interconnect trees in Al metallization technology.I was very fortunate for several summer internship opportunities during my gradu-ate studies. The thermal analysis work using ANSYS originated during my internshipat IBM T. J. Watson Research Center in Summer 2003. I am grateful to Kathryn W.Guarini and Meikei Ieong for giving me the opportunity to design the pilot testchipin 3D IC technology at IBM Watson Research.My graduate school experience has been truly rewarding, both from academicand professional perspective. MIT fosters professional development and growth of itsgraduate student community through numerous programs and activities. I was the7Academics, Research, and Careers Committee Chair of the Graduate Student Councilduring the 2002-2003 academic year. I managed and led a group of graduate studentsin organizing major programs such as MIT Career Fair, Airport Shuttle Program,International Student Mentorship Program, Travel Grant Program, Academic CareersSeries, and Professional Development Lecture Series. I would like to thank every oneat the Graduate Student Council, and in particular, Emmi Snyder, for the wonderfulexperience.Most importantly, I am indebted to the support and encouragement I have receivedover the years from my parents and family. I am grateful to my wife, Raiyan T.Zaman, for her love and dedication. I would like to thank my brother, Syed MasudulAlam, for his assistance in drawing many figures and for his support while writingthis thesis.8Contents1 Introduction 231.1 Interconnect Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . 241.1.1 Electromigration Phenomenon . . . . . . . . . . . . . . . . . . 251.1.2 Electromigration Failure Modes . . . . . . . . . . . . . . . . . 271.1.3 Immortality Condition . . . . . . . . . . . . . . . . . . . . . . 281.1.4 Electromigration Lifetime Model . . . . . . . . . . . . . . . . 301.2 Interconnect Architecture Schemes . . . . . . . . . . . . . . . . . . . 311.2.1 Aluminum Metallization Technology . . . . . . . . . . . . . . 311.2.2 Copper Metallization Technology . . . . . . . . . . . . . . . . 311.3 Fundamental Reliability Unit . . . . . . . . . . . . . . . . . . . . . . 321.4 Three-Dimensional (3D) Integrated Circuit Technology . . . . . . . . 341.4.1 Technology Concept . . . . . . . . . . . . . . . . . . . . . . . 341.4.2 Layout Methodology for 3D Circuits . . . . . . . . . . . . . . 351.4.3 3D IC Technology with Thermal Management . . . . . . . . . 361.4.4 Interconnect Reliability in 3D ICs . . . . . . . . . . . . . . . . 381.5 Circuit-Level Reliability Analysis . . . . . . . . . . . . . . . . . . . . 391.5.1 Electromigration Reliability in Networked Interconnects (ERNIand ERNI-3D) . . . . . . . . . . . . . . . . . . . . . . . . . . 401.6 Thesis Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411.7 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Hierarchical Reliability Analysis Flow 452.1 Electromigration Experiments . . . . . . . . . . . . . . . . . . . . . . 4592.2 Via Asymmetric Failure Characteristics in Copper Technology . . . . 472.3 Steps in Hierarchical Reliability Analysis for Copper Metallization . . 492.4 Contrast with Hierarchical Reliability Analysis in Aluminum Metal-lization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.5 Electromigration Default Model . . . . . . . . . . . . . . . . . . . . . 532.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Electromigration Reliability Mathematics 573.1 Basic Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.2 Lifetime Distribution Model . . . . . . . . . . . . . . . . . . . . . . . 613.2.1 Lognormal Distribution . . . . . . . . . . . . . . . . . . . . . . 623.3 Reliability Mathematics in Series and Parallel Systems . . . . . . . . 633.4 Reliability Metrics for Full-chip Analysis . . . . . . . . . . . . . . . . 653.4.1 Probability of no failure . . . . . . . . . . . . . . . . . . . . . 663.4.2 Failure Rate along chip lifetime . . . . . . . . . . . . . . . . . 663.4.3 Time to cumulative % failure . . . . . . . . . . . . . . . . . . 673.5 Reliability Metrics in Use . . . . . . . . . . . . . . . . . . . . . . . . 673.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 Electromigration Reliability Comparison of Aluminum and CopperInterconnects 714.1 Immortality Condition Filters . . . . . . . . . . . . . . . . . . . . . . 724.2 Diffusivity Mechanisms and Models . . . . . . . . . . . . . . . . . . . 734.2.1 Diffusion in Aluminum Interconnects . . . . . . . . . . . . . . 734.2.2 Diffusion in Copper Interconnects . . . . . . . . . . . . . . . . 754.2.3 Diffusivity Comparison . . . . . . . . . . . . . . . . . . . . . . 764.3 Lifetime Comparison of Straight Line Interconnects . . . . . . . . . . 784.4 Reliability Prediction Using the ITRS . . . . . . . . . . . . . . . . . . 814.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82105 SysRel: Circuit-Level Reliability CAD Tool 855.1 Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 855.2 Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . 865.3 Circuit Layout Parsing . . . . . . . . . . . . . . . . . . . . . . . . . . 885.4 Interconnect Tree Extraction . . . . . . . . . . . . . . . . . . . . . . . 905.5 Reliability Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . 915.6 Simulation with 32-bit Comparator Layout . . . . . . . . . . . . . . . 935.6.1 Copper Metallization Technology . . . . . . . . . . . . . . . . 955.6.2 Aluminum Metallization Technology . . . . . . . . . . . . . . 965.7 Implications of SysRel . . . . . . . . . . . . . . . . . . . . . . . . . . 965.8 Three-Dimensional IC Analysis in SysRel . . . . . . . . . . . . . . . . 975.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006 Cell-Based Reliability Analysis in SysRel 1016.1 Cell Characterization in SysRel . . . . . . . . . . . . . . . . . . . . . 1026.2 Hierarchical Layout Support in SysRel . . . . . . . . . . . . . . . . . 1036.3 Cell-based Reliability Simulation . . . . . . . . . . . . . . . . . . . . 1046.4 Computational Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . 1066.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 Non-blocking Via Analysis in Copper Metallization Technology 1097.1 Non-blocking Via Due to Liner Ruptures . . . . . . . . . . . . . . . . 1107.2 Non-blocking Via Assignment in Circuit Layout . . . . . . . . . . . . 1117.3 Steps for Non-blocking Via Analysis in SysRel . . . . . . . . . . . . . 1127.4 Interconnect Tree Merging . . . . . . . . . . . . . . . . . . . . . . . . 1147.5 Line-length Effect on Reliability . . . . . . . . . . . . . . . . . . . . . 1167.6 32-bit Comparator Layout Simulation . . . . . . . . . . . . . . . . . . 1187.7 Discussion of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120118 Thermal-Aware Reliability Analysis in SysRel 1238.1 Fundamental Concepts for Thermal Analysis . . . . . . . . . . . . . . 1248.2 Thermal Simulation with ANSYS . . . . . . . . . . . . . . . . . . . . 1278.3 Transient Thermal Behavior in Integrated Circuits . . . . . . . . . . . 1318.4 Cell-based Thermal Profiling Technique . . . . . . . . . . . . . . . . . 1348.5 Interconnect Joule Heating . . . . . . . . . . . . . . . . . . . . . . . . 1388.6 Thermo-file Implementation in SysRel . . . . . . . . . . . . . . . . . 1408.7 Thermal-Aware Reliability Simulation with 32-bit Comparator . . . . 1418.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429 Reliability Analysis with Arithmetic and Logic Unit 1459.1 Arithmetic and Logic Unit Design and Synthesis . . . . . . . . . . . . 1459.2 Reliability Simulation with Different Metallization Technologies . . . 1489.3 Thermal-Aware Reliability Analysis with the 64-bit ALU . . . . . . . 1529.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15510 Conclusions and Future Work 15710.1 Summary and Implications of Results . . . . . . . . . . . . . . . . . . 16010.1.1 SysRel: Interactive Reliability CAD Tool . . . . . . . . . . . . 16010.1.2 Thermal-Aware Reliability Analysis in SysRel . . . . . . . . . 16310.1.3 Reliability Comparison of Copper and Aluminum Metallizations 16410.1.4 Non-blocking Via Analysis with Copper Metallization . . . . . 16510.2 Potential Applications of SysRel . . . . . . . . . . . . . . . . . . . . . 16610.3 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16710.3.1 Optimization of SysRel . . . . . . . . . . . . . . . . . . . . . . 16710.3.2 Enhanced Electromigration Lifetime Model . . . . . . . . . . . 16810.3.3 Thermal Analysis and Management in 3D IC Technology . . . 16910.3.4 Impact of Process Variations . . . . . . . . . . . . . . . . . . . 170A SysRel Source Code Overview 171A.1 Main Application Classes . . . . . . . . . . . . . . . . . . . . . . . . . 17112A.2 Graphical Interface Classes . . . . . . . . . . . . . . . . . . . . . . . . 172A.3 File Parser Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173A.4 Corner-stitched Data-structure Classes . . . . . . . . . . . . . . . . . 175A.5 Layout and Tree Representation Classes . . . . . . . . . . . . . . . . 175A.6 Reliability Computation Class . . . . . . . . . . . . . . . . . . . . . . 177B Cadence to ANSYS Geometric Model Conversion: cds2inp 179C Matlab Source Code for TProfile 189D SysRel Release 193D.1 SysRel v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193D.2 SysRel v2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931314List of Figures1-1 Cross-section of an Integrated Circuit showing multi-layer metal inter-connects on top of a device layer. . . . . . . . . . . . . . . . . . . . . 241-2 Gate and interconnect delay, and interconnect reliability requirementin different technology generations . . . . . . . . . . . . . . . . . . . . 251-3 Electromigration-induced failure modes . . . . . . . . . . . . . . . . . 271-4 Immortality Condition in a straight line interconnect . . . . . . . . . 281-5 Interconnect architecture schemes . . . . . . . . . . . . . . . . . . . . 321-6 Example of an interconnect tree, the fundamental reliability unit forelectromigration analysis . . . . . . . . . . . . . . . . . . . . . . . . . 331-7 Cross-section of a 3D IC with 3D trees and inter-wafer vias . . . . . . 351-8 Different types of vias/contacts for 3D ICs . . . . . . . . . . . . . . . 361-9 Thermal management using optimal placement of microfluidic thermalconnects in a face-to-face and back-to-back bonded 3D IC. . . . . . . 371-10 Flow diagram of the hierarchical circuit-level reliability analysis in ERNI 401-11 A screen-shot of MAJIC with a view of menu items for reliability anal-yses in ERNI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412-1 Schematic diagrams of designed interconnect trees for electromigrationtesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462-2 Side-view schematic of void formation in via-above and via-below in-terconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482-3 Calculating Lmax in an interconnect tree. . . . . . . . . . . . . . . . . 503-1 Failure Rate versus time for typical Integrated Circuits (bathtub curve). 60153-2 Schematic illustration of various system reliability models . . . . . . . 644-1 Cross-section of an Al interconnect with schematic illustration of dif-fusion pathways . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744-2 Cross-section of a Cu interconnect with schematic illustration of diffu-sion pathway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754-3 A composite model of atomic diffusivity versus interconnect line width 774-4 Atomic diffusivity of Al and Cu metallization technologies at differenttemperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784-5 Interconnect lifetimes of various types of lines in Cu and Al metalliza-tion technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804-6 Cross-over temperature versus current density plot . . . . . . . . . . 804-7 Interconnect lifetimes of various types of lines in Cu and Al metalliza-tion technologies in typical operating condition . . . . . . . . . . . . . 815-1 Screen shot of SysRel’s desktop pane . . . . . . . . . . . . . . . . . . 875-2 Corner-stitched representation of a single plane with multiple tiles ina Magic layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895-3 Extraction of an interconnect tree from corner-stitched representationof tiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915-4 Reliability analysis flow diagram in SysRel . . . . . . . . . . . . . . . 925-5 The 32-bit comparator circuit layout analysis in SysRel . . . . . . . . 945-6 Layout technique for Al polygranular to bamboo type conversion in aninterconnect line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975-7 The 3D 32-bit comparator circuit layout for SysRel reliability simulation 996-1 The largest cell, FAX1, characterization with SysRel . . . . . . . . . 1036-2 Hierarchical layout view in SysRel . . . . . . . . . . . . . . . . . . . . 1046-3 Cell-based adder layout’s level 2 view in SysRel . . . . . . . . . . . . 1057-1 Multi-level Cu interconnects with different liner thicknesses . . . . . . 110167-2 Straight line via-to-via Cu dual-damascene test structure for electro-migration experiments . . . . . . . . . . . . . . . . . . . . . . . . . . 1117-3 Menu options for reliability analysis in SysRel with non-blocking viasin a circuit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137-4 Schematic illustration of interconnect tree merging with a non-blockingvia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147-5 Dynamic conversion of a non-blocking via into fully blocking in amerged tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157-6 Illustration of interconnect tree merging in a 3-input nand gate layout 1167-7 Time-to-failure dependence on interconnect length . . . . . . . . . . . 1177-8 Mortal trees in the 32-bit comparator circuit layout when all vias areassigned non-blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207-9 Test structures to investigate the line length dependence of reliabilityin Cu interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218-1 Z-axis dimensions with a substrate height of 10um in cds2inp . . . . 1288-2 ANSYS thermal simulation with a bulk CMOS transistor . . . . . . . 1308-3 Energy dissipation in the NMOS transistor of an inverter at differentoutput frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318-4 MOSFET transient temperature plot at 2.5MHz square wave heatgeneration frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328-5 MOSFET transient temperature plot at 1GHz square wave heat gen-eration frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338-6 Package-level thermal modeling to compute uniform temperature atthe bottom surface of a substrate . . . . . . . . . . . . . . . . . . . . 1358-7 Thermal impulse response at the top surface of a substrate . . . . . . 1368-8 Power density profile of an inverter cell in a 30um× 30um substrate . 1378-9 Temperature profile calculated using TProfile of an inverter cell in a30um× 30um substrate . . . . . . . . . . . . . . . . . . . . . . . . . 1378-10 Modeling the temperature profile in a straight line interconnect . . . 138178-11 Modeling the temperature rise due to joule heating in multi-level in-terconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408-12 Thermo-file menu options in SysRel for thermal-aware reliability analysis1418-13 Layout-level non-uniform temperature profile in the 32-bit comparatorcircuit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429-1 The 64-bit Arithmetic and Logic Unit layout in Magic . . . . . . . . . 1479-2 Immortality in interconnect trees in the 64-bit ALU circuit with Cumetallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489-3 Nonuniform temperature profile of the 64-bit ALU circuit in bulkCMOS technology at V dd = 5V and operating frequency= 250MHz . 15310-1 Straight line interconnect and interconnect tree structures in circuitlayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15810-2 Screen shot of SysRel desktop pane . . . . . . . . . . . . . . . . . . . 16110-3 Multiple vias at a junction in wide metal interconnects . . . . . . . . 169B-1 Cadence circuit layout to ANSYS geometry conversion . . . . . . . . 18018List of Tables3.1 Tree types with lognormal lifetime distribution . . . . . . . . . . . . . 683.2 Improved tree types with lognormal lifetime distribution . . . . . . . 683.3 Full-chip reliability metrics of circuit layout with various types of mor-tal trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684.1 Reported (jL) product thresholds for immortality conditions in Al andCu technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.2 Immortality length in various technology generations with Al and Cumetallizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734.3 Material parameters used for calculating diffusivity of Al polygranulartype lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744.4 Material parameters used for calculating diffusivity of Al bamboo typelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754.5 Material parameters used for calculating diffusivity in Cumetallizationtechnology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764.6 Technology-specific parameter description and values for lifetime cal-culation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794.7 Worst case interconnect lifetimes of various types of Cu and Al lines . 825.1 Menu bars and corresponding operations in SysRel . . . . . . . . . . 885.2 A sample .mag layout file . . . . . . . . . . . . . . . . . . . . . . . . 895.3 SysRel simulation results of hierarchical reliability analysis with Cumetallization in the 32-bit comparator circuit layout . . . . . . . . . . 95195.4 SysRel simulation results of hierarchical reliability analysis with Almetallization in the 32-bit comparator circuit layout . . . . . . . . . . 965.5 SysRel simulation results of hierarchical reliability analysis with Cumetallization in the 3D 32-bit comparator circuit layout . . . . . . . . 986.1 Cell reliability characterization data format in sysrelcell.char file . . . 1026.2 Statistics of Fundamental Reliability Units in the 4-bit adder layout . 1056.3 Statistics of Fundamental Reliability Units in the 32-bit comparatorcircuit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066.4 Time required for layout drawing in SysRel . . . . . . . . . . . . . . . 1076.5 Time required for extracting interconnect trees in SysRel . . . . . . . 1076.6 Computational efficiency with cell-based reliability analysis in SysRel 1077.1 Input parameters for non-blocking via analysis defined in sysrel.emparamfile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127.2 Reliability simulation with various degrees of non-blocking vias in the32-bit comparator circuit layout . . . . . . . . . . . . . . . . . . . . . 1198.1 Electrical and thermal analogy for modeling steady-state heat flow . . 1258.2 Material parameters for thermal simulation in ANSYS . . . . . . . . 1298.3 Maximum temperature increase due to interconnect joule heating indifferent technology generations . . . . . . . . . . . . . . . . . . . . . 1408.4 Thermal-aware reliability simulation results with Cu metallization inthe 32-bit comparator circuit layout . . . . . . . . . . . . . . . . . . . 1439.1 Operations in the 64-bit Arithmetic and Logic Unit . . . . . . . . . . 1469.2 The number of cells of various types in the 64-bit ALU circuit . . . . 1479.3 Full-chip reliability analysis with the 64-bit ALU in different metalliza-tion technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499.4 Times to void nucleation and void growth in various interconnect tech-nologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151209.5 Cu atomic diffusivity requirements for equivalent circuit-level reliabil-ity in the 64-bit ALU with Al and Cu metallizations . . . . . . . . . 1519.6 Thermal-aware full-chip reliability report for the 64-bit ALU with Cu/SiO2metallization in bulk CMOS technology . . . . . . . . . . . . . . . . . 1549.7 Thermal-aware full-chip reliability report for the 64-bit ALU with Cu/SiO2metallization in SOI technology . . . . . . . . . . . . . . . . . . . . . 1552122Chapter 1IntroductionIn the pursuit of higher performance and integration, Integrated Circuit (IC) technol-ogy is heading towards the nanotechnology era. The gate length of a state-of-the-artactive device, such as a metal oxide silicon field-effect transistor (MOSFET), is in therange of 45 to 50 nm allowing millions of such devices to be fabricated in a singlechip [1]. In addition to achieving higher density, smaller devices increase speed due tohigher drive current during the “on” state. While more and more devices are desirablefor integrating more functionality in a single chip, interconnecting the devices usingmetal wires takes up an even greater percentage of space. The on-chip metal linesreferred to as interconnects are fabricated by deposition of metal and dielectric mate-rials, lithography of patterned features, and selective etching. ICs can have up to 14layers of metal interconnects as predicted by the International Technology Roadmapfor Semiconductors (ITRS) 2003 edition (figure 1-1) [2]. The dielectric material, re-ferred to as inter-layer dielectric (ILD), provides insulation between interconnects andmechanical stability for the multi-level interconnect structure.Concurrent to device dimension scaling, interconnect width is shrinking while totalinterconnect length is increasing exponentially. According to the International Tech-nology Roadmap for Semiconductors, 688 meters of active metal wiring per centimetersquare area are required to construct a high-performance chip in 2004. Interconnectdelay related to its resistance (R), capacitance (C), and in some cases inductance(L) has become dominant over gate delay as shown in figure 1-2(a). Moreover, the23Figure 1-1: Cross-section of an Integrated Circuit showing multi-layer metal intercon-nects on top of a device layer. Source: the ITRS [2].increased capacitance in interconnects leads to an increase in net switching power.Since the invention of ICs, Aluminum (Al) and its alloys have been used in the met-allization layers. Silicon Dioxide (SiO2) is used as the ILD material. Copper (Cu)has been replacing Al as the material of choice for interconnects due to its lowersheet resistance while new ILDs with lower dielectric constant (low-k dielectrics) areunder active study. However, as seen in figure 1-2(a), interconnect delay is still dom-inant with the introduction of Cu and low-k dielectrics beyond 180nm technologygenerations. Therefore, interconnect design and analysis have become as importantas device design [3].1.1 Interconnect ReliabilityFrom the interconnect design perspective, reliability is the extent to which the inter-connects maintain signal integrity and produce desired functionality over the lifetime24600 500 400 300 200 100Generation (nm)(a)403020100Delay (ps)gates and Al/SiO2Al/SiO2gates and Cu/low-kCu/low-ktotal gate delay4000 6000 8000 10000 12000Total Interconnect Length (m/cm )2Year 20012002200320042005200620071.21.00.80.60.4(FIT s/m length/cm )x102-2(b)Figure 1-2: (a) Gate and interconnect delay in different technology generations [4].(b) Interconnect reliability requirement versus total interconnect length in differentyears. Here FIT refers to Failure Unit. Source: the ITRS 2001 edition [2].of a chip. Stress conditions, such as current density and temperature, during cir-cuit operation affect the interconnect reliability. As the performance of present dayICs increases, a more stringent operating condition in the metal interconnects is ex-pected with a service temperature of 105oC and maximum current density of 0.5MA/cm2 [2]. In addition, the interconnect reliability requirement has become morestringent as shown in figure 1-2(b). Electromigration is the primary interconnectreliability concern.1.1.1 Electromigration PhenomenonElectromigration is the transport of atoms in a conducting material due to momentumtransfer from flowing electrons. When a difference in electrical potential is applied toan interconnect, electrons flow from low potential (cathode) to high potential (anode)terminal. The metal atoms start to diffuse along the electron flow direction due toscattering. Assuming that the electron flow direction has a positive sign, the “electronwind” force on atoms can be expressed asFelec = −q∗E = −Z∗eρj (1.1)25where q∗ = Z∗e is the effective atomic charge, Z∗ is the effective atomic chargenumber, e is the fundamental electron charge, E = ρj is the electric field, ρ is theelectrical resistivity of the metal, and j is the current density. As current densityopposes the electron flow direction, a negative sign for j attributes to a positive signin Felec.In an interconnect terminating at diffusion barriers such as Tungsten (W ) filledvias or Tantalum (Ta) liners, the “electron wind” force creates tensile stress near thecathode where the atoms deplete and compressive stress near the anode where theatoms accumulate [5]. The resulting stress gradient leads to a mechanical drivingforce, referred to as the back-stress force, which opposes the electromigration windforce. The back-stress force is expressed asFmech = Ωdσdx(1.2)where Ω is the atomic volume, σ is the stress, and x is the distance measured alongthe length of the line. Due to a negative value of dσdx, Fmech has a negative value whichis consistent with our sign convention here.According to the 1-D Korhonen model [6], the atomic flux, Ja, can be expressedas a function of Felec and Fmech usingJa =DCakT(Felec + Fmech)=DCakT(−Z∗eρj + Ωdσdx)= −DCakT(Z∗eρj − Ωdσdx) (1.3)where Ca is the atomic concentration, D is the atomic diffusivity, k is the Boltzmann’sconstant, and T is the temperature. Equation 1.3 suggests that |Felec| > |Fmech| isrequired to have a non-zero atomic flow for electromigration.261.1.2 Electromigration Failure ModesA void nucleates at the cathode end of an interconnect line when the tensile stress ex-ceeds the critical stress necessary for void nucleation, σcrit nuc. Once a void nucleates,it can grow to larger volume even spanning the whole interconnect width as shown infigure 1-3(a). In both Al and Cu metallization schemes, void nucleation and growthwould result in a resistance increase of the line. In the event of a fully spanningvoid, conductive refractory metal under layers or over layers in Al technology willshunt the current to prevent an open-circuit failure. An open-circuit failure is morecommon in Cu technology due to the absence of conductive refractory layers. Whilean open-circuit due to voiding would cause functional failure, the resistance increasewould add extra delay in signal propagation resulting in timing violations in timingcritical circuits.Figure 1-3: Electromigration-induced failure modes; (a) Tensile stress at the cathode-end of an interconnect can cause voiding [7]; (b) Compressive stress at the anode-endcan cause extrusion [8].Compressive stress at the anode end of both Cu and Al interconnect lines cancause metal extrusion where the atoms accumulate (figure 1-3(b)). However, extru-sions are not observed in service operating condition for either Al or Cu as metalinterconnects are surrounded by rigid ILD material that suppresses the formation ofhillocks. Current densities greater than 5 MA/cm2 are required to observe extrusionduring electromigration testing condition [9]. Therefore, voiding is the primary mode27of electromigration failure in ICs.1.1.3 Immortality ConditionIn steady state, the “electron-wind” force balances the back-stress force resultingin zero atomic flux and a linear time-invariant stress along the interconnect line asillustrated in figure 1-4 [10]. Equation 1.3 in steady state becomesZ∗eρj = Ωdσdx(1.4)tensilecompressiveSideviewTopviewcathode anodeStress evolution with time (c)(b)(a)σcrit_nucσcritxFmech∂∂Ω=σje-ZFelec*= ρσoσextFigure 1-4: Immortality Condition in a straight line interconnect. (a) Side view (b)Top view (c) Stress as a function of location along the interconnect at different times.Rewriting equation 1.4 for a straight line interconnect with length, L, we can get28an expression for current density and line length product (jL)jL =Ω∆σmaxρeZ∗(1.5)where ∆σmax is the maximum stress difference between the cathode and anode ends.If the stress at the cathode end is σcrit, ∆σcrit can be written as∆σcrit = 2(σcrit − σo) (1.6)Assuming the initial stress, σo, is zero,∆σcrit = 2σcrit (1.7)If the critical tensile stress for void nucleation, σcrit nuc, is greater than the maximumsteady state tensile stress, σcrit, developed at the cathode end, no void will form andthe line will not fail. Using equation 1.5, we can derive a critical current density linelength product (jL) that defines the immortality condition asjL < (jL)crit nuc =Ω∆σcrit nucρeZ∗(1.8)which means short lines or lines stressed at low current densities that satisfy (jL) <(jL)crit nuc are immune from void nucleation, and thus “immortal” from void nucle-ation limited failure.On the other hand, if (jL) exceeds (jL)crit nuc, a void will nucleate in the metalline. However, if the void does not completely block the current flow, the void nucle-ation will not be fatal. In the presence of conducting over layers and under layers, thevoid can continue to grow as the current is shunted around it through the refractorymetal layers until the electron wind force and back-stress balance again. Under suchcircumstances, the line is immortal if the resistance increase associated with the voidvolume is lower than the maximum acceptable resistance increase, ∆Rmaxcrit , and themaximum compressive stress in the line does not cause yielding or fracture of the sur-29rounding dielectric material. The immortality condition due to resistance saturationis given by [11](jL)crit sat =ρAρlAl∆RmaxcritR2ΩBZ∗eρ(1.9)where ρ and A are the resistivity and cross sectional area of the high-conductivitymetal, respectively, ρl and Al are the resistivity and cross sectional area of the shuntlayer, respectively, and R is the initial resistance of the line. It is apparent that(jL)crit sat > (jL)crit nuc as resistance saturation will occur after void nucleation.1.1.4 Electromigration Lifetime ModelElectromigration testing is conducted at accelerated conditions with temperaturesas high as 300oC and current densities greater than 2.0 MA/cm2. To estimate thelifetime of a population of interconnects at service conditions, the well known Black’sequation is used to extrapolate the median-time-to-failure (MTTF) to service condi-tions [12]. Black’s equation is expressed ast50 = Aj−neEakT (1.10)where A is a constant independent of temperature and current density, j is the currentdensity, n is the current density exponent, Ea is the activation energy for the rate-limiting diffusion path, k is the Boltzmann’s constant, and T is the temperature. Acurrent density exponent n = 1 is consistent with void growth limited failure sincethe rate of unconstrained void growth is proportional to the current density [13]. Anexponent n = 2 indicates void nucleation limited failure in the model based on theKorhonen analysis [6]. Although variations of the original Black’s model have beenproposed in [14, 15], Black’s equation is still generally used to estimate the lifetimeof an interconnect due to electromigration.301.2 Interconnect Architecture SchemesAl and Cu are the primary choices of metal for interconnects in modern day ICs.IBM introduced Cu technology in commercial ICs in 1998. Since then, Cu has beenreplacing Al as the material of choice for interconnects due to its lower sheet resis-tance. While the electromigration behavior of Al interconnects is quite well under-stood [16, 17], the reliability of Cu is still under active study. Due to the differences inchemical properties between Cu and Al, the fabrication process for Cu interconnectsis drastically different from that for Al interconnects. The differences in processingand architecture schemes lead to the differences in electromigration reliability.1.2.1 Aluminum Metallization TechnologyAs illustrated in figure 1-1, metal interconnects are surrounded by ILD materials mostcommonly SiO2. Al chemically reacts with SiO2 to form alumina, which eliminatesatomic diffusion of Al into the surrounding ILD and along the interface betweenAl and SiO2. As a result, Al metallization is processed by a subtractive etchingmethod in which the patterned lines are formed by etching the deposited blanket Alfilm. Architecturally, Al interconnects have thick, highly electromigration-resistantrefractory metal layers, which are usually made of Titanium Nitride (TiN), servingas anti-reflection coatings at the top of the lines (see figure 1-5(a)). Similar underlayers have also been included, which serve as seed layers for the via-fill process.Tungsten (W ) filled vias are used to connect layers of Al metallization. Metal underand over layers serve as shunt for electron flow andW -filled vias serve as fully blockingboundaries for electromigration.1.2.2 Copper Metallization TechnologyCu does not chemically reduce SiO2 like Al does. Furthermore, a suitable etchant forCu thin films is unavailable for commercial use. Consequently, Cu interconnects arefabricated by the damascene method, in which a trench is first etched into a blanketlayer of ILD before filling it with Cu by electroplating. Since Cu undergoes field31Figure 1-5: Interconnect architecture schemes; (a) Al interconnect, with W -filled viasand conducting shunt layers at the top and bottom of the interconnect line. (b) Dual-damascene Cu interconnect, with Cu-filled vias, thin refractory liners at the sides andbottom of the line, and a dielectric capping layer at the top of the line.enhanced diffusion in most dielectric materials (including SiO2), in order to preventCu atoms diffusing into the device layer, thin refractory metal layers consisting ofTantalum (Ta) or Tantalum Nitride (TaN) are placed at the sides and bottom of theCu interconnect lines (See figure 1-5(b)). The Cu lines are capped with a dielectricdiffusion barrier, which is usually made of Silicon Nitride (Si3N4). Cu-filled vias areused to connect multiple layers of metallization.1.3 Fundamental Reliability UnitAn important concept in hierarchical reliability analysis is the classification of Funda-mental Reliability Units (FRU). By definition, an FRU is a component in reliabilityanalysis, contributing to the underlying failure mechanism, which can be treated in-dependently from other such components. During a hierarchical reliability analysis,FRUs are first identified and extracted from a circuit layout. FRU based reliabilityanalysis reduces the complexity of the problem and provides the flexibility of addingnew failure units for different reliability phenomena.Straight line via-to-via structures are used for most electromigration experimental32work. However, in real circuits, multiple straight line segments are connected at junc-tions and many such junctions are connected within the same layer of metallization.An “interconnect tree” is a unit of continuously connected high-conductivity metal ly-ing within one layer of metallization terminating at the vias or diffusion barriers [18].An example of an interconnect tree is shown in figure 1-6.Figure 1-6: Example of an interconnect tree, the fundamental reliability unit for elec-tromigration analysis.It has been established that an interconnect tree is the appropriate fundamen-tal reliability unit for the circuit-level reliability assessment of Al-based metalliza-tion [18]. The fully blocking boundaries formed at the W -filled vias confine atomicdiffusion within an interconnect. Materials within an interconnect tree can diffusefreely between the segments and the stress evolutions in different segments of a treeare coupled.On the other hand, Cu-filled vias with thin liner material at the bottom in Cumetallization technology may or may not act as fully blocking boundary for atomicdiffusion [10]. Liner ruptures have been observed in some experimental work whichallow materials to freely diffuse between different layers of metallization. In suchcases an interconnect tree cannot be treated as the fundamental reliability unit forCu-based technology.331.4 Three-Dimensional (3D) Integrated Circuit Tech-nologyTechnology scaling has posed limitations on overall system performance by degradingthe interconnect delay, increasing the power consumption due to interconnect capac-itance, and increasing the number of longer global and semi-global lines in a chip.The need for a long-term solution to enhance performance in successive technologygenerations is apparent. One such long-term solution is the three-dimensional (3D)Integrated Circuit technology.1.4.1 Technology ConceptThe main idea behind 3D integration is to form multiple device layers along the thirdaxis (z axis) and lower the interconnect lengths by connecting the devices in theselayers vertically. This has been accomplished by bonding multiple wafers fabricatedwith different or similar technologies [19, 20] as well as by fabricating multiple devicelayers on the same wafer [21, 22] using the epitaxial growth of Si. In a wafer bondingtechnology, each device-interconnect layer is fabricated separately on different waferswith the same or different technologies, and then the wafers are bonded with eachother using a bonding layer of Cu, polymeric adhesives, or plain oxide-to-oxide (ILDmaterial) bond.The wafers in a 3D stack are electrically connected using high aspect ratio viasor contacts. When bonding is complete, 3D ICs have vertical interconnects of sig-nificantly longer length than vias or contacts in conventional or 2D ICs. Moreover,the 3D circuits fabricated with a wafer bonding technology have two different typesof vertical interconnects as shown in figure 1-7. The Cu-filled inter-wafer vias con-nect multiple interconnect trees from different wafers. At the bonding surface, theadjacent metallization layers from two wafers can also be connected with vertical Culines. The vertical Cu lines create a new type of trees, referred to as a “3D tree”,which expands between two different wafers.34Figure 1-7: Cross-section of a 3D IC with 3D trees and inter-wafer vias. Here DLand MLs correspond to device and metal layers, respectively.Although the concept of 3D integration emerged as early as 1979 [23], significantresearch work was done only after the early 90’s as the limitations of technologyscaling became apparent. 3D integration is an attractive solution as it can signifi-cantly reduce the number of long wires by mapping a 2D circuit into different lay-ers [24]. Moreover, the total number of repeaters for long and intermediate wires willalso decrease, resulting in a higher density and lower interconnect-limited chip area.Consequently, high-performance microprocessors and programmable logic devices areattractive applications for 3D integration.Another promising advantage of 3D integration is its ability to integrate heteroge-neous technologies into a single 3D chip. Future system-on-chip (SOC) applicationswill consist of digital, analog, RF, and optical components on the same die [25]. Using3D integration, each unit can be fabricated on separate wafers with its own optimizedprocess technology, and then integrated vertically to form a 3D SOC [19, 20].1.4.2 Layout Methodology for 3D CircuitsWe developed a comprehensive layout methodology for 3D ICs and implemented itin 3D-Magic [26, 27]. In order to facilitate the layout of 3D ICs, all inter-wafer viasor contacts are generalized into three major categories. The three categories of viasare sufficient for defining almost all types of interconnection between wafers in a 3DIC. Figure 1-8 shows the three categories of vias; connected-to-top, connected-to-bottom, and through-wafer vias. Categorizing vias in such a way allows the layoutmethodology to be flexible enough to support different types of bonding schemes,35such as face-to-face, face-to-back, or back-to-back1.A 3D contact pointConnected-to-top ViaThrough-Wafer ViaConnected-to-bottom ViaTopBottomFigure 1-8: Different types of vias/contacts for 3D ICs.The availability of 3D-Magic has led to interesting research with a wide range oflayout-specific circuit analyses, from performance comparison of 2D and 3D circuitsto layout-specific reliability analyses in 3D circuits. Using 3D-Magic, researchers havedesigned and simulated an 8-bit encryption processor mapped into 2D and 3D FPGAlayouts [28]. The layout methodology has been adopted for 3D CAD tool researchat MIT [29] . It has built the bridge between synthesis and layout tools for 3Dcircuits and allowed the demonstration of physical layouts of circuits produced by the3D place and route tool. Moreover, it is an essential element of a novel ReliabilityComputer Aided Design (RCAD) tool, ERNI-3D [26].1.4.3 3D IC Technology with Thermal ManagementWhile 3D IC technology has its advantages, extracting heat generated by power dissi-pation in inner wafers is quite a challenge. Conventional packaging technology allowsheat extraction from one side, typically the Si-substrate side, by attaching a Cu heatspreader and fin heatsink. When using such a method for heat extraction, heat fluxfrom wafers further away from the heatsink would flow through the 3D stack leading1Face-to-face bonding refers to bonding metal interconnect side of a wafer to the metal intercon-nect side of another wafer while forming the 3D IC stack. Back-to-back bonding refers to bondingSi-substrate side of a wafer to the Si-substrate side of another wafer in forming the 3D IC stack.36to an increased power density on a smaller footprint. Therefore, temperature rise in3D circuits can be significantly higher than that in conventional ICs [30].Flexibility in bonding schemes, such as back-to-back and face-to-face, can be ex-ploited to address thermal management in 3D ICs. We proposed a vision for 3D ICtechnology that efficiently incorporates thermal management [31]. Figure 1-9 presentsthe main idea in such a 3D IC technology.to External PinsThrough-wafer viaHeatSinkDeviceLayer 4DeviceLayer 3DeviceLayer 2Metal Layer1 & 2DeviceLayer 1 Top view of thermalconnect and through-wafer interconnectBack-to-Back bond-through-wafer electricalconnections and-Thermal connects formicro-channel fluid flowFace-to-Face bond withhigh density of bondedinterconnectFigure 1-9: Thermal management using optimal placement of microfluidic thermalconnects in a face-to-face and back-to-back bonded 3D IC.Starting at the bottom of the stack, there is a face-to-face bond between the firsttwo wafers. This face-to-face bond allows high-density inter-wafer connection andeliminates area trade-off between through-wafer via and active devices that is presentin back-to-back (substrate-to-substrate) or face-to-back bonding. In the figure, thereare through-wafer vias through the substrate of the first wafer to get signals out for theconnections to external pins. The number of such through-wafer vias is comparableto the number of pins and significantly lower than that of inter-wafer vias at a high-37density face-to-face bond.Next, wafer no. 2 is bonded with wafer no. 3 using a back-to-back bond. This back-to-back or substrate-to-substrate bond results in a bonded silicon interface which canbe used to contain micro-channels, termed thermal connects, for heat removal withfluid flow. The thermal connects or micro-channels are wet-etched in the back ofthe individual substrates before bonding. The thermal connects can be criss-crossedamong through-wafer vias, as shown in figure 1-9, as well as laid out manually witha higher density at the chip hotspots.The 3D stack can grow further upward using a face-to-face bond with wafer no. 3.In figure 1-9, the topmost wafer is wafer no. 4 and its substrate is connected to a heatsink/heat removal device. As it is apparent from the structure, every wafer in the3D stack except wafer no. 1, has a heat removal device connected to its substrate.Therefore, thermal connects can also be placed in the substrate of wafer no. 1 whilebonding to the package. Thus, every wafer in a 3D stack has heat removed throughits substrate and the heat removal problem can be reduced to that of a conventional2D IC.1.4.4 Interconnect Reliability in 3D ICsElectromigration phenomenon and reliability concerns described in section 1.1 areequally applicable to 3D circuits. In addition to treating interconnect trees as thefundamental reliability unit, special attention is required for the through-wafer andinter-wafer vias in 3D circuits. Through-wafer vias can be significantly longer inheight than conventional vias as illustrated in figure 1-9. The reliability impact dueto increased height as well as the presence of a bonded interface is under activeinvestigation [32]. Depending on the failure characteristics observed in through-waferand inter-wafer vias, it may be necessary to treat them as additional fundamentalreliability units in 3D ICs.As discussed earlier, the stack effect in 3D circuits can potentially increase theservice temperature of the interconnects. According to equation 1.10, MTTF ofan interconnect tree is exponentially dependent on its temperature. Due to high38power dissipation, high temperature rise is already of great concern in modern dayconventional ICs. Consequently, the 3D counterparts of such chips are expected topose a greater reliability challenge due to higher temperature.1.5 Circuit-Level Reliability AnalysisThe conventional approach to meet reliability goals in an integrated circuit has beento use simple and conservative design rules based on current density in a wire segment.However, this simplicity and conservatism lead to limited performance in newer tech-nology generations [18]. Models and techniques have been developed to make realisticreliability assessments of interconnects during the design and layout process (Relia-bility Computer Aided Design, RCAD), so that the reliability data can be fed back,and changes can be made promptly before the fabrication process to achieve optimumreliability and performance. BERT (BErkeley Reliability Tool) [33], iTEM [34], ERNI(Electromigration Reliability in Networked Interconnects) [35], and ERNI-3D [27] areexamples of reliability analysis tools for Al-based interconnect technology that havebeen previously developed.BERT and iTEM calculate the overall reliability of a given layout based on thereliability estimations from individual straight line segments. However, the reliabil-ity of a segment depends strongly on the activities in the linked segments. In otherwords, segments can not be treated as independent reliability units. Interconnecttrees need to be considered as the fundamental reliability units as discussed in sec-tion 1.3. Another limitation in BERT and iTEM is the lack of immortality checkingin interconnect segments. As illustrated in section 1.1.3, not all interconnect treesare prone to electromigration failure. Neglecting immortality condition in intercon-nect trees leads to redundant computation in analysis, and more importantly, leads tooverly conservation and incorrect reliability estimates. ERNI and ERNI-3D addressesthe limitations of earlier tools.391.5.1 Electromigration Reliability in Networked Interconnects(ERNI and ERNI-3D)The RCAD tool ERNI (Electromigration Reliability in Networked Interconnects),developed at MIT [35], allows process-sensitive and layout-specific reliability assess-ments of a fully or partially laid-out integrated circuit. Figure 1-10 shows the flowdiagram of ERNI’s operations. First, the interconnect trees are extracted from a Extract Reliability Units from Layout Apply Filters to Eliminate "Immortal" Units Apply Simple, Conservative Default Models for Reliability Calculate Reliability Budget, Rank Unreliable Units Redo Layout? Simulation of Circuit Operation Model Library Simulate Reliability of Least Reliable Units End Figure 1-10: Flow diagram of the hierarchical circuit-level reliability analysis in ERNI.circuit layout and categorized into mortal and immortal trees based on the currentdensity and line length product (jL). Further computation goes on with only themortal trees, and a reliability figure for each tree, in terms of MTTF, is obtainedafter applying the default electromigration model [18].The code for ERNI is written in Java 2 (JDK 1.2). It is a client extension toMAJIC, a layout parser and viewer also written entirely in Java [36]. Lots of data-structures and algorithms in MAJIC are based on MAGIC, an IC layout editor de-veloped at UC Berkeley and widely used in academia [37]. Using MAJIC, users canview a circuit layout, and apply reliability analysis by choosing different filtering algo-rithms from the “ERNI” menu. Figure 1-11 shows a screen-shot of MAJIC with thedisplay of available options in the “ERNI” menu. ERNI operates on 2D IC layoutswith multiple metallization layers created using MAGIC.The reliability analysis concept in ERNI has been extended to develop a distinct40Figure 1-11: A screen-shot of MAJIC with a view of menu items for reliability analysesin ERNI.RCAD tool, ERNI-3D, for the reliability analysis of 3D circuits [27]. Using ERNI-3D, circuit designers can get interactive feedback on the reliability of their circuitsassociated with electromigration, 3D bonding, and joule heating. ERNI-3D parses 3Dcircuit layouts from 3D-Magic and extracts both conventional and 3D interconnecttrees from the layouts. It employs the hierarchical reliability analysis approach usedin ERNI and applies a simplistic joint probability distribution method to report asingle reliability figure for the whole chip. The initial version of ERNI-3D treats 3Dcircuits with two wafers or device-interconnect layers in the stack. Both ERNI andERNI-3D are capable of reliability analysis of only Al-based interconnect technology.1.6 Thesis StatementThe goal of this thesis is to develop new methodologies for interconnect reliabilityanalysis and a reliability CAD tool, SysRel (System-level IC Reliability), for circuit-level electromigration analysis with Cu as well as Al metallization technologies inconventional and 3D circuits. Much insight has been gained through electromigrationexperiments with Cu dual-damascene technology to identify its distinctive behaviorsand a set of circuit-level reliability rules [10]. SysRel is capable of reliability assess-ment and comparison of Cu and Al metallizations in a circuit layout. As experimental41reliability work and lifetime models only deal with individual reliability units, a setof full-chip reliability matrices, based on a joint probability distribution of individualunits, has been proposed and implemented in SysRel. Such a system-level view ofreliability analysis allows users to identify electromigration critical nets in a circuitlayout and quantify their impact on full-chip reliability.While a comprehensive reliability analysis tool, such as SysRel, is desirable, it isequally important to integrate the tool into existing IC design flows. Large ICs aredesigned using a cell/module-based hierarchy. The concept of cell/module level reli-ability characterization has been introduced in SysRel which, in addition to allowingeasy integration into existing design flows, significantly reduces the computationalload during reliability assessment of a large layout with numerous reliability units.In other design scenarios where layout is fully custom and not necessarily cell-based,SysRel and its methodologies are still applicable.Reliability is a strong function of chip temperature. Therefore, a cell-based sub-strate thermal profiling method is developed and implemented in SysRel to estimatethe non-uniform layout-level temperature due to cell power dissipations. Using thenon-uniform substrate temperature as a boundary condition, interconnect joule heat-ing is taken into account while calculating the lifetimes of mortal reliability units.In addition to a technology-generic feature, such as thermal analysis, SysRel hasthe capability of non-blocking via analysis specific to Cu metallization technology.Users can investigate the impact of non-blocking vias on full-chip reliability withboth stochastic and deterministic assignment of non-blocking vias in a layout. Thisnovel analysis has provided valuable insight into electromigration test structure designin Cu dual-damascene technology.1.7 Organization of ThesisThe thesis consists of ten chapters and four appendices. Chapter 2 describes the hi-erarchical electromigration reliability analysis flow with fundamental reliability unitsin the context of Cu and Al metallization technologies. After extracting fundamental42reliability units from a circuit layout, (jL) product filtering algorithms with specificproperties for Cu and Al metallizations are applied to identify immortal trees. Adefault model is applied to compute the lifetimes of individual mortal units. Chapter3 describes the concepts in reliability mathematics that are applied to derive the pro-posed full-chip reliability metrics using the lifetimes of individual failure units. Thereliability mathematics coupled with the full-chip metrics give rise to the concept ofreliability budget in circuit layout.In Chapter 4, the electromigration behaviors of Cu and Al metallization technolo-gies are compared. Using the current density and temperature projections from theITRS, relative reliability of the two metallization technologies is presented in detail.Chapter 5 introduces the RCAD tool, SysRel, and presents the reliability simulationresults from a 2D and 3D 32-bit comparator circuit analysis.Chapter 6 describes the methodology for cell-based reliability analysis in SysRel.The advantages of cell-based reliability analysis are demonstrated using the simulationresults from the 32-bit comparator circuit’s hierarchical layout. Chapter 7 introducesthe non-blocking analysis in Cu metallization technology, and describes the relatedcapabilities and underlying algorithms in SysRel. Simulation results with the 32-bitcomparator layout with varying degrees of non-blocking vias are discussed.Chapter 8 outlines a layout-level thermal profiling technique implemented in Sys-Rel for estimating the temperature rise in 2D circuits. Device-level thermal simulationwork with ANSYS2, leading to insights for the proposed technique, is also discussed.Chapter 9 describes the design of a significantly large circuit, 64-bit Arithmetic andLogic Unit (ALU). The ALU circuit has been simulated to investigate the reliabilityissues with various metallization technologies and the impact of temperature on full-chip reliability. Future reliability issues with Cu/low-k interconnect technology arealso explored.Finally, Chapter 10 summarizes the results of the thesis and outlines future re-search directions in interconnect reliability CAD area. The appendices include rele-vant Matlab code, information on Java classes in SysRel, and SysRel software release.2ANSYS is a comprehensive engineering simulation tool available from ANSYS Inc.4344Chapter 2Hierarchical Reliability AnalysisFlowIn actual integrated circuits, various types of interconnect trees exist and their com-plexities can be greater than the test structures for electromigration experiments.While it is impossible to fabricate and test all the possible interconnect trees found inan IC, a set of rules and specifications can be developed to make realistic reliabilityassessments of interconnects during the design and layout process. Based on insightsgained from the experimental work with various Cu interconnect trees, a hierarchicalreliability analysis approach for circuit-level and layout-specific reliability assessmentof any Cu interconnect network has been proposed in [10, 38].This chapter briefly presents the experimental work for electromigration analysisand summarizes the distinct reliability characteristics in Cu metallization technol-ogy. The hierarchical reliability assessment flow is also discussed step-by-step andcompared with that of Al metallization technology.2.1 Electromigration ExperimentsGan et al. conducted electromigration experiments with Cu dual-damascene tech-nology [10, 39]. The experimental procedure for Cu electromigration was dividedinto multiple stages: test structure design, sample fabrication, packaging, testing45and failure analyses. Figure 2-1 shows a sample of test structures: straight via-to-via interconnects (‘I’), straight via-to-via lines with an additional via at the center(‘dotted-I’), straight via-to-via lines with an additional metal limb at the center (‘T’),straight via-to-via lines with two additional metal limbs at the center (‘+’), straightvia-to-via lines with a transition in width along the interconnect (‘width-transition’)and wider straight via-to-via lines with extra metal limbs nearer to one side of thelines (asymmetrical ‘T’ transition). The test lines are either in the first (M1) orsecond (M2) level of metallization.Figure 2-1: Schematic diagrams of designed interconnect trees for electromigrationtesting (a)‘I’ (b) ‘dotted-I’ (c) ‘T’ (d) ‘+’ (e) asymmetric ‘T’ transition (f) width-transition.Test samples were fabricated using a Cu dual-damascene process in IME andSEMATECH. Sixteen samples of each test structure were stressed in a package-levelelectromigration test system with a temperature range between 50oC and 400oC.To reduce the possibility of temperature-induced failures and variation in diffusivitydue to joule heating, current densities were chosen to limit joule heating below 10oCthrough out the experiments. The range of current density in the test structures wasbetween 0.5 to 5.0 MA/cm2.46In addition to recording median-time-to-failure (t50) (defined as time to 30% in-crease in resistance), resistance trends were observed for different structures. Variousfailure analysis tools, such as Optical Microscopy, SEM, FIB and TEM, were used tocharacterize the type of failure modes. In the experiments, all failures detected weredue to open-circuit failure from formation of voids in a line or via. Experimentalresults and failure characteristics are presented in detail in [39, 40, 41, 42].2.2 Via Asymmetric Failure Characteristics in Cop-per TechnologyIn Cu interconnects, it has been widely reported that the Cu/Si3N4 interface actsboth as the dominant diffusion pathway for atoms and as the likely site for voidnucleation. Due to this fact, the lifetimes of M1 type interconnects are different fromthat of M2 type interconnects [40]. Gan et al. experimentally demonstrated thatthe lifetimes of the M2 test structures were always higher than those of the M1 teststructures, provided that both types of interconnects had the same length, width, andnumber of vias at each end. The underlying phenomenon applies to all metal layersand can be generalized using via-above and via-below definitions. The via-above teststructures refer to interconnect segments which lie in the first level of metallization,and the vias are located above the test lines. Conversely, the via-below test structuresare in the second metallization level while the vias are located below the test lines(see figure 2-2).During electromigration in Cu interconnects, a tensile stress develops at the cath-ode end, where the Ta liner underneath a via forms a blocking boundary to thediffusing Cu atoms. For current Cu technology, the critical tensile stress for voidnucleation has been estimated to be 41 MPa or less [43]. In via-below structures,voids preferentially nucleate at the Cu/Si3N4 interface due to the low critical stressrequired for that interface. An open-circuit failure would occur only when the voidgrows to span the whole thickness of the metal line, resulting in a very large void47Figure 2-2: Side-view schematic of void formation in via-above and via-below inter-connects. (a) A small-volume fatal void in via-above interconnects; (b) A large-volumepartially-spanning non-fatal void in via-below interconnects.volume as shown in figure 2-2(b). On the other hand, in via-above structures themaximum tensile stress develops at the Cu/Si3N4 interface near the cathode via.Therefore, an open-circuit failure would occur if a small-volume void forms below thevia, such that the pathway for electron flow is blocked (see Figure 2-2(a)).This asymmetry in the void volume required for failure not only accounts forthe asymmetry in lifetime but also contributes to the different (jL)crit products inimmortality conditions for via-above and via-below type of interconnects. The (jL)critvalues are directly related to the critical stresses required for interconnect failure.The values are reported by Ho et al. to be 3700 A/cm for via-below [44, 45], and byHau-Riege to be 2100 A/cm for via-above type interconnects [43]. Therefore, in Cumetallization technology, if the electrons are flowing into the line from a via on top, ashorter lifetime and a smaller (jL)crit is expected compared to the condition in whichthe electrons flow into the line from below.482.3 Steps in Hierarchical Reliability Analysis forCopper MetallizationThe hierarchical reliability analysis is based on extracting interconnect trees, thefundamental reliability units; applying various stages of filtering conditions to identifymortal units; and then applying a default model to estimate lifetimes of the mortalunits. The input to this flow is a circuit layout with mask definitions. The steps forhierarchical reliability analysis in Cu metallization technology are as follows.(i) Extract interconnect trees from a layout: As defined in section 1.3, an in-terconnect tree is a unit of continuously connected high-conductivity metal lyingwithin one layer of metallization. In addition to geometric properties, the lo-cations of the vias/contacts are also identified in each interconnect tree. Givenan interconnect tree in Cu metallization, every via is classified as either “via-above” or “via-below” depending on whether it is located above or below theinterconnect line, respectively.(ii) Determine the longest terminating via-to-via distance, Lmax: When an in-terconnect tree is constructed from multiple segments as shown in figure 2-3,multiple terminating vias exist due to vias at the end of each segment. To findthe longest distance between two terminating vias in an extracted tree, an in-terconnected graph needs to be created where vias and via-to-via distances arerepresented as nodes and edges, respectively. The shortest path between thevias are calculated using the Minimum Spanning Tree algorithm [46]. Then ter-minating via-to-via distances are just the addition of via-to-via distances alongthe path. Lmax is chosen to be the longest terminating via-to-via distance.(iii) Filter interconnect trees using via-above (jL)crit nuc failure criterion: Thefirst step of the filtering algorithm assumes the worst case scenario. The maxi-mum current density allowed by the design rule, jmax, can be obtained from theInternational Technology Roadmap for Semiconductors [2]. Using the worst casethreshold of (jL)crit nuc = 1500A/cm [47] (i.e. the via is above the line at the49LmaxFigure 2-3: Calculating Lmax in an interconnect tree.cathode end as in a M1 test structure), it is checked whether (jL)crit nuc/jmax >Lmax for every interconnect tree. If the inequality is true, the tree is consideredimmortal and is ignored during further analysis.(iv) Filter mortal trees using via-below (jL)crit sat failure criterion: Determineif either of the vias contributing to Lmax is a via-above. If at least one of the viashappens to be via-above, then the interconnect tree may fail with a via-above(jL)crit nuc failure criterion as determined in the previous step and the hierarchi-cal flow proceeds directly to step (v). However, if both of the vias are via-below,the via-below (jL)crit sat failure criterion of (jL)crit sat = 3700A/cm [44, 45] isapplied. The condition (jL)crit sat/jmax > Lmax is checked for such interconnecttrees. However, even if a tree passes this test, all the other vias in the tree mustbe considered before classifying it as immortal. This is because via-above nodeshave a much smaller immortality value and thus shorter lengths may fail. Thelongest distance in the graph from any via-above node to all other vias, Lmax va,is determined. We again apply the test (jL)crit nuc/jmax > Lmax va to determinewhether the tree might fail.(v) Estimate the current density, ji, in each segment: The Vdd and Gnd linesin the circuit layout need to be identified as they have unidirectional current flowand are most susceptible to electromigration failure. Most local interconnectstransmit signals between devices in the form of bidirectional or alternating cur-50rent (AC). In these cases, an equivalent direct current (DC) which produces thesame electromigration damage [48], such as the root-mean-square (RMS) of theAC, is assumed. On the other hand, clock signals usually operate with pulsedDC. Experiments [48] and modeling [49] have shown that the equivalent DC isgiven by the average of the pulsed DC, Iavg, which is given by the expressionIavg = rI =(tonton + toff)I (2.1)where I is the current during the “on” time and r is the duty ratio given by tonand toff where ton is the pulse width and the sum of ton and toff equals the clockperiod. The worst case loading of Vdd and Gnd lines can be identified usingpower consumption reports from a circuit simulation tool. However, estimatingcurrent flow at each segment in local interconnects is complicated and requiresdetailed circuit-level simulation.(vi) Filter mortal trees by detailed calculation of steady-state stresses: Theconcept of steady-state stresses in interconnect trees is an extension of the im-mortality condition in stud-to-stud straight lines. The maximum stress differ-ence in an interconnect tree, ∆σmax, is given by the path that has the highestsum of the (jL) products, summing over the limbs/segments in the path [18].This is expressed by∆σmax =ρeZ∗Ω(jL)eff (2.2)where(jL)eff = maxall junction pairs i, j(∑kjkLk)(2.3)where ∆σmax is the stress difference between the anode and the cathode, Z∗is the effective charge number, e is the elementary charge, ρ is the electricalresistivity of the metal, Ω is the atomic volume, i and j are two terminatingvias, and jk and Lk are the current density in, and length of, segment k alongthe path between i and j, respectively. To filter the immune interconnect treesusing (jL)eff , repeat steps (iii) and (iv) by replacing (jL)max with (jL)eff .51(vii) Analyze mortal trees with electromigration failure models: A conserva-tive default electromigration model based on the analysis of individual nodes(vias or contacts) in a tree is used to estimate the lifetime of a mortal tree. Theoutput of the model is taken to be the median-time-to-failure of a tree. Thedefault model is discussed in a later section. Furthermore, numerical methodscan be applied for detailed calculation of the time-dependent stress analysis.Software programs, such as MIT/EmSim [9, 50] and CuEmSim [51] , allow thecalculation of stress evolution in multi-terminal interconnect trees.(viii) Apply full chip stochastic reliability model: The median-time-to-failure(MTTF) or t50 of each mortal interconnect tree is estimated using the de-fault model or a micro-structure level electromigration simulation program (e.g.MIT/EmSim). The full-chip reliability model combines the t50 of multiple inter-connect trees from the same layout and provides a set of reliability metrics forthe overall chip. The stochastic model and underlying reliability mathematicsare discussed in the next chapter.2.4 Contrast with Hierarchical Reliability Analy-sis in Aluminum MetallizationFailure mechanisms in Cu and Al interconnects are significantly different due totheir different architectural schemes as described in section 1.2. In Al metallizationstructures, the Al line has refractory metal layers above and below, and tungsten (W )filled vias are used to connect interconnects from different levels. TheW -filled vias actas a perfect and symmetric diffusion barrier irrespective of the electron flow direction.Therefore, lifetime differences were not observed for M1 and M2 type structures inAl metallization.Via classification is not required in hierarchical analysis flow for Al technology.Steps (iii) and (iv) in the hierarchical reliability analysis are merged into one where asingle (jL) product threshold, (jL)sat = 4000A/cm, is applied to check for immortal-52ity [11]. The reported (jL) product threshold for Al is also slightly higher than that ofCu via-below type interconnects. This is because Al interconnect architecture allowsfor top and bottom conducting shunt layers to divert electron flow around voids forboth M1 and M2 type of geometry.2.5 Electromigration Default ModelWhile microstructure level simulation of electromigration in complex interconnecttrees is possible, less computationally-intensive analytical models are needed forcircuit-level reliability assessment.A conservative model for the analysis of interconnect trees has been previouslyproposed by Hau-Riege and Thompson [18] and verified for Al-based test structures.Such a model is extended, by Gan, for Cu interconnect analysis [41]. The stressevolution at a node (x = 0) in an interconnect tree has been conservatively estimatedasσ(t) =√4tπρeZ∗Ω√BΩkT∑iDiji∑i√Di+ σo (2.4)where B is the bulk modulus of the material surrounding the migrating material, σo isthe initial hydrostatic stress in the tree, and Di and ji are the atomic diffusivity andcurrent density in segment i, respectively. Assuming a constant and time-independentatomic diffusivity along the segment and initial hydrostatic stress, σo = 0, we canestimate the time, tnucl, when the tensile stress is equal to the critical stress for voidnucleation, σnucl, at the node.tnucl =σnuclΩρeZ∗√π4√kTBΩ∑i√Di∑iDiji2(2.5)The above equation can be used to calculate time to extrusion, textru, using the criticalstress for extrusion, σextru, at the node.textru =σextruΩρeZ∗√π4√kTBΩ∑i√Di∑iDiji2(2.6)53At each via, the stress evolution of the whole subtree connected to the node isconsidered. Each subtree is then replaced with a semi-infinite limb with an effectivediffusivity and current density. Once a void nucleates, it starts to grow and leads toa resistance increase in one of the limbs. Assuming that the void spans the wholewidth and thickness of the interconnect, the void length is written as a function oftime, using which, time to void growth, tgrow, to length Lv can be expressed as,tgrow =LvkTρeZ∗1∑iDiji(2.7)Equations 2.5, 2.6, and 2.7 are described in detail in [41]. All the vias in an inter-connect tree are evaluated individually using the equations. The methodologies forestimating the lifetime of an interconnect tree, using the vias’ tnucl, tgrow, or textru,for Cu and Al technologies are as follows.Derivation of tree’s time-to-failure (TTF): Cu technology1. For each via in a tree2. if (via-above)3. TTF = tnucl4. if (via-below)5. TTF = min(tnucl + tgrow, textru)6. Tree’s TTF = min(all via TTFs)Derivation of tree’s time-to-failure (TTF): Al technology1. For each via in a tree2. TTF = min(tnucl + tgrow, textru)3. Tree’s TTF = min(all via TTFs)54It is important to note that extrusion has not been observed to be the primarycause of failure for both circuit operating and accelerated testing conditions (j <5MA/cm2). Therefore, (tnucl + tgrow) is calculated as the TTF of via-below typenodes in Cu technology and for all nodes in Al technology.2.6 SummaryWe have described a new hierarchical approach for predicting the reliability of Cu-based interconnects in circuit layouts. Based on the differences in electromigrationfailure mechanisms from Al technology observed in experimental work, a (jL) productfiltering algorithm with a classification of separate via-above and via-below treatmentsare applied to Cu interconnects. Such a via classification is not required in Al met-allization technology. After the filtering of immortal trees, a default model is appliedto the remaining trees to compute a reliability figure, in terms of time-to-failure, forindividual units.5556Chapter 3Electromigration ReliabilityMathematicsTime-to-failure of an interconnect tree needs to be modelled as a stochastic variable.The operating stress conditions leading to failure and degradation of physical environ-ment, such as grain structure and texture, are not deterministic. In this chapter basicprobability terms essential for understanding stochastic reliability analysis are firstdefined. Electromigration failure times are found in many studies to approximate alognormal distribution. While models and experiments aid in predicting the lifetimeof a single unit, it is more important to quantify the impact on full-chip reliability asa large number of failure units can exist in a circuit. Therefore, probability theoriesin series and parallel systems are reviewed and brought into the perspective of ICreliability analysis. Finally, a set of reliability metrics, based on the desired lifetimeof the chip, has been proposed and demonstrated for full-chip reliability analysis.3.1 Basic DefinitionsThere are four basic probability functions that are the fundamental building blocksof reliability mathematics. These are cumulative distribution function, reliabilityfunction, probability density function, and failure rate.If time-to-failure, TTF, of a failure unit is a continuous time random variable, the57probability that the unit will fail within time t is called the Cumulative DistributionFunction (CDF) and denoted by F (t). Mathematically,F (t) = P(TTF ≤ t) (3.1)Conversely, the probability that the unit will survive beyond time t is called theReliability Function and denoted by R(t). Mathematically,R(t) = 1− F (t) (3.2)It is important to understand the physical meaning of the CDF from the perspective ofreliability experiments. Suppose that N identical components are put into operationat the same instant (t = 0) and operate for a time t. If the number of componentsfailing is Nf (t) at time t, the fraction of population failing is Nf (t)/N . This ratio isregarded as an attribution of a single such component by defining it as the CDF, i.e.F (t) =Nf (t)N(3.3)The above statement can be made with the number of surviving components beyonda time t to define the Reliability Function as equation 3.2. Both R(t) and F (t) aredimensionless quantities between 0 and 1.For a continuous random variable the Probability Distribution Function (PDF) isdefined asf(t) =dF (t)dt(3.4)A TTF distribution model can be any probability density function defined over therange of time from t = 0 to t =∞. According to equation 3.4, f(t)dt is the probabilitythat a component will fail between time t and t + dt; and CDF F (t) can be derivedby integrating f(t) until a time t. Mathematically,F (t) =∫ t0f(x)dx (3.5)58and therefore, ∫∞0f(t)dt = 1 (3.6)In light of the above discussion, the CDF F (t) can be described in the followingthree ways.Definition 1 F (t) = the area under the PDF f(t) from 0 to t.Definition 2 F (t) = the probability that a single randomly chosen new unit will failby time t.Definition 3 F (t) = the proportion of the entire population that fails by time t.The latter two definitions are particularly useful in interpreting the joint CDF in thepresence of multiple failure units as we will see in a later section.While Cumulative Distribution Function, Probability Distribution Function, andReliability Function are the fundamental building blocks of reliability mathematics,most literature makes the greatest use of the Failure Rate. The Failure Rate is definedfor non repairable populations as the (instantaneous) rate of failure for the survivorsto time t during the next instant of time [52]. It is a rate per unit of time similarin meaning to reading a car speedometer at a particular instant and seeing 45 mph.The next instant the Failure Rate may change and the units that have already failedplay no further role since only the survivors count.The Failure Rate is denoted by λ(t) and calculated asλ(t) =f(t)1− F (t) =f(t)R(t)(3.7)As seen from the expression, it is the conditional probability that a t hour-old unitwill fail in an additional time dt. λ(t) has a unit of [time]−1. For a well-designedsystem, Failure Rate, in terms of number of units per hour, can be very small. As aresult, special units are commonly used. In the IC industry, Failure Rates are mostcommonly expressed in FITs, which is an abbreviation for Failure unIT [53]. Bydefinition, FIT is parts per million per thousand hours, also referred to as PPM/K.59Therefore,1 FIT = 1 in 1, 000, 000 failures per 1000 hours1 FIT = 1 in 1, 000, 000, 000 failures per hourWhen λ(t) is expressed in failures per hour, the Failure Rate in terms of FIT can beobtained byFIT ≡ λ(t)× 109 (3.8)The typical Failure Rate of an integrated circuit generally varies as a function oftime in the manner illustrated in figure 3-1 [52, 53, 54]. During the early life of anFailure RatetimeEarly Failure Steady State Wear OutFigure 3-1: Failure rate versus time for typical Integrated Circuits (bathtub curve).IC the failure rate is high and decreasing over time. This period is often referredto as “early failure” or “infant mortality”. The cause of early failures are generallymanufacturing defects. Rigorous tests (burn-in tests) are performed on ICs right aftermanufacturing to weed-out early failures and produce high quality chips. During thesteady-state period, the Failure Rate is fairly low and constant over time as a resultof large number of unrelated causes. Eventually ICs enter the wearout period where60the Failure Rate is monotonically increasing. The electromigration induced failure ofinterconnects is an example of a wearout process.3.2 Lifetime Distribution ModelSeveral probability distribution functions have been successfully used to characterizelifetimes arising from a wide range of failure mechanisms. Following are some widelyused lifetime distribution models.• Exponential• Weibull• Extreme Value• LognormalThe lifetime distribution model can be chosen based on the physics of failure mecha-nism and empirical success in fitting actual failure data. However, choosing a modelby fit alone is not sufficient as many distributions are flexible enough to fit a widerange of failure analysis data.Electromigration failure times are found in many studies to approximate a log-normal distribution. Moreover, lognormal distribution is appropriate for a failuremechanism with the multiplicative degradation property. If at any instant in time adegradation process undergoes a small increase in the total amount of degradationthat is proportional to the current total amount of degradation, then it is reasonableto expect the time to failure (i.e. reaching a critical amount of degradation) to followa lognormal distribution [55].Let x1, x2, · · ·xn be measurements of the amount of degradation for a particularfailure process taken at successive discrete instants of time as the process movestowards failure. Assume the following relationships exist between the xs:xi = (1 + ǫi)xi−1 (3.9)61where ǫi are small, independent random perturbations to the system that move thefailure process along. Equation 3.9 is referred to as the multiplicative degradation ina failure mechanism. The total amount of degradation at the n-th instant of timecan be expressed byxn =(n∏i=1(1 + ǫi))x0 (3.10)where x0 is initial state and the ǫi are small random perturbations. Taking the naturallogarithm of both sides,lnxn =n∑i=1ln(1 + ǫi) + lnx0 =n∑i=1ǫi + lnx0 (3.11)Using the Central Limit Theorem argument we can conclude that lnxn has a normaldistribution, and therefore, xn will follow a lognormal distribution for any n or at anyt in continuous time [52]. Diffusion or migration of atoms are expected to follow themultiplicative degradation property which in turn justifies the wide use of lognormaldistribution for electromigration.3.2.1 Lognormal DistributionWhen the natural logarithm of a random variable X is normally distributed withmean µ and variance σ2, X is said to have a lognormal distribution. The relation-ship between normal and lognormal distribution allows us to analyze lognormallydistributed data with methods for normal distributions. A lognormal random vari-able X can be transformed to a standard normal variable Z where Z = (lnX−µ)/σ.The Cumulative Distribution Function of the lognormal distribution, F (t), is thenF (t) = Φ(ln t− µσ)(3.12)where Φ is the Cumulative Distribution Function of the standard normal distributiondefined byΦ(t) =12π∫ t−∞e−u22 du (3.13)62The Probability Density Function, f(t), of the lognormal distribution is given byf(t) =1σt√2πe−12σ2(lntt50)2(3.14)andt50 = eµ (3.15)where t50 is the median-time-to-failure (MTTF). Therefore, two parameters are re-quired to fully define a lifetime model with lognormal distribution: the t50 or median-time-to-failure (MTTF) and σ standard deviation (STD).3.3 Reliability Mathematics in Series and ParallelSystemsMultiple failure units exist in a circuit layout each with its own lifetime distribution.To derive a single lifetime distribution applicable to the whole layout, system levelreliability mathematics is required.A series system is shown in figure 3-2(a). Each block represents an individualfailure unit. The following three assumptions are needed to apply a series systemreliability model.1. Each component operates or fails independently of every other one, at leastuntil the first component failure occurs.2. The system fails when the first component failure occurs.3. Each of the n (possibly different) components in the system has a known lifetimedistribution model Fi(t).Assumption no. 2 above suggests the time-to-failure of the system, tf , is the minimumvalue of the individual times-to-failure, ti.tf = min(t1, t2, t3, · · ·) (3.16)63When the series model assumption holds, system Reliability Function, Rs(t), Cumu-lative Distribution Function, Fs(t), and Failure Rate, λs(t) are computed as follows.Rs(t) =n∏i=1Ri(t) (3.17)Fs(t) = 1−n∏i=1(1− Fi(t)) (3.18)λs(t) =n∑i=1λi(t) (3.19)The subscript i refers to the i-th component in a series system with total n compo-nents. If Fs(t) is the same type of function as Fi(t), it is said to be self-reproducing.The lognormal distribution is not self-reproducing, so that if Fi(t) are lognormal, thenFs(t) cannot be lognormal, and vice versa [54]. The distribution of the series systemwith lognormal unit distribution is often called the multi-lognormal distribution [56].(a) (b) (c)Figure 3-2: Schematic illustration of various system reliability models; (a) seriesmodel; (b) parallel model; (c) complex model.In contrast to a series model, for which the first component failure causes thesystem to fail, is a parallel model for which all the components have to fail beforethe system fails. If there are n components, any (n − 1) of them may be consideredredundant to the remaining one (even if the components are all different). Figure 3-2(b) shows a diagram of a parallel system. The following three assumptions areneeded to apply parallel system reliability model.1. Each component operates or fails independently of every other one.2. The system operates as long as at least one component is still operating. System64failure occurs at the time of the last component failure.3. Each of the n (possibly different) components in the system has a known lifetimedistribution model Fi(t).Assumption no. 2 above suggests the time-to-failure of the system, tf , is the maximumvalue of the individual times-to-failure, ti.tf = max(t1, t2, t3, · · ·) (3.20)When the parallel model assumptions hold, the system Cumulative Distribution Func-tion, Fp(t) is calculated as follows.Fp(t) =n∏i=1Fi(t) (3.21)with the subscript i referring to the i-th component. The system Reliability Function,Rp(t), and Failure Rate, λp(t), can be evaluated using basic definitions, once we haveFp(t).Systems encountered in real life are not often as simple as just a series or parallelmodel. Rather they can be a combination of series and parallel models an exampleof which is shown in 3-2(c). Such systems are analyzed with a bottom up approachapplying series or parallel model on components and sub-components.3.4 Reliability Metrics for Full-chip AnalysisElectromigration failure dictates the long range lifetime of a chip as the underlyingmechanism is a wear out process. While the lifetimes of individual failure units areassumed to have lognormal probability distribution, it is important to derive a setof full-chip stochastic metrics useful to designers. Moreover, different chips wouldhave different reliability goals vis-a-vis their applications. For example, the reliabilitytarget for a chip inside a mobile phone, typically used for 3 to 4 years, might be verydifferent than that of an ear implant chip.65We propose a set of full-chip metrics based on the desired lifetime of a chip [38].Given a target lifetime Tl, reliability metrics useful to designers are: probability of nofailure, FIT along lifetime, maximum FIT, and time to cumulative % failure. Tak-ing the time-to-failure estimated using the default electromigration model (describedin section 2.5) as median-time-to-failure, t50, and standard deviation, σ, from ex-perimental results, we model the lifetimes of individual interconnect trees using thelognormal distribution. For full chip reliability analysis, it is conservatively assumedthat all the failure units are in series, i.e. the chip will fail when any one of the unitsfails. Lognormal distribution is not self-reproducing for a series system and the pro-posed metrics do not require any probability distribution assumption on the full-chiplifetime. The derivation procedures for the metrics are described next.3.4.1 Probability of no failureThe probability of no failure until lifetime Tl is essentially the value of the full-chipReliability Function Rf (t) at t = Tl. As a series system model is assumed, the full-chipReliability Function can be calculated asRf (t) =n∏i=1Ri(t) (3.22)where Ri(t) is the Reliability Function of the i-th component in a circuit layout withn mortal interconnect trees. Ri(t) of each component is derived usingRi(t) = 1− Fi(t) (3.23)where the lognormal Cumulative Distribution Function Fi(t) of i-th component iscalculated using equation 3.12.3.4.2 Failure Rate along chip lifetimeAccording to the series system model, the full-chip Failure Rate, λf (t), is the summa-tion of each mortal interconnect tree’s Failure Rate, λi(t). The Failure Rate of each66unit is calculated using the definition,λi(t) =fi(t)1− Fi(t) (3.24)where fi(t) and Fi(t) are the lognormal Probability Density and Cumulative Distri-bution Functions, respectively. The full-chip failure rate is converted into FIT andplotted against the desired lifetime of the chip. The maximum FIT along the lifetimeis also reported.3.4.3 Time to cumulative % failureUnlike the Failure Rate and Reliability Function, time to cumulative % failure doesnot have a closed form expression particularly for a series system with lognormalprobability units. According to the definition no. 3 of the Cumulative DistributionFunction, F (t) is the proportion of the entire population that fails by time t. There-fore, once the full-chip Cumulative Distribution Function Ff (t) is derived, time toany cumulative % failure can be read from the plot where the x-axis range of 0 to 1represents 0% to 100% of the population and y-axis is the time-to-failure.3.5 Reliability Metrics in UseLet us assume that a circuit layout has two types of trees, type 1 and type 2, withmedian-time-to-failures (t50) and standard deviations (σ) for lognormal distributionas defined in table 3.1. Given that the target lifetime, Tl, of the chip is 30 years,probability of no failure Ri(Tl) and maximum FIT of each type of trees are shown aswell in the table.The median-times-to-failure of the two types of trees are significantly larger incomparison to the target lifetime of 30 years. However, the impact of an individualunit becomes obvious only when full-chip reliability is considered. Full-chip probabil-ity of no failure within target lifetime, Rf (Tl), is the product of Ri(Tl) (equation 3.22).Rf (Tl) can be low with multiple type 2 trees in a layout. Full-chip FIT is the sum-67mation of individual unit’s FIT which is also a large value with few type 1 trees in alayout.Table 3.1: Tree types with lognormal lifetime distribution.t50 (years) σ Ri(Tl) max FITTree Type 1 145 1.59 0.8391 747.40Tree Type 2 2000 1.6 0.9957 30.4075The two techniques for improving full-chip reliability, from a mathematical per-spective, are increasing t50 and reducing σ. While t50 of individual trees can be in-creased with circuit design and layout techniques, such as reducing current flow andincreasing line width, σ is often dictated by process variations and micro-structure ofmaterials. Circuit level reliability enhancement techniques will be further discussedin chapter 5. Assuming that the t50 of type 1 tree is improved to 300 years and σ oftype 2 tree is reduced to 0.80, the new Ri(Tl) and max FITs are shown in table 3.2.Now let us consider full-chip reliability of a circuit layout with a total of seven mortalTable 3.2: Improved tree types with lognormal lifetime distribution.t50 (years) σ Ri(Tl) max FITImproved Tree Type 1 300 1.59 0.9262 361.224Improved Tree Type 2 2000 0.8 1.00 0.0020units with combinations of three type 1, four type 2 trees and three improved type 1,four improved type 2 trees. The full-chip reliability metrics are reported in table 3.3for each combination. The improvement in full-chip reliability is significant.The above example demonstrates the significance of the proposed full-chip metricsTable 3.3: Full-chip reliability metrics of circuit layout with various types of mortaltrees. Here target lifetime of the chip is 30 years.Mortal inter-connect treecombinationProbabilityof no failuremax FIT time to 50%failuretime to 0.2%failure3 Type 1 + 4 Type 2 0.5807 2315.3 37.88 years 0.875 years3 Improved Type 1 +4 Improved Type 20.7946 1083.7 81.5 years 1.82 years68in identifying the impact of individual unit based on desired lifetime of the chip. More-over, a designer has the flexibility to choose any particular metric, such as probabilityof no failure, max FIT, or time to any cumulative % failure, as the figure of meritdepending on the chip’s application. FIT is more widely used in the ITRS predictionswhile time to 0.02% failure is the figure of merit for selected applications [57].3.6 SummaryThis chapter gives an introduction to probability mathematics used in reliabilityanalysis and describes the lognormal probability distribution widely accepted for anelectromigration lifetime model. While models and experiments aid in predictingthe lifetime of a single unit, it is more important to quantify the impact on full-chip reliability as a large number of failure units can exist in a circuit. Therefore,probability theories in series and parallel systems are reviewed. To understand theimpact of an individual failure unit on full-chip reliability, it is important to have aset of reliability metrics. Electromigration failure essentially dictates the long rangelife-time of a chip. We propose to conduct full-chip reliability analysis based on atarget lifetime, Tl. Given a target lifetime Tl, reliability metrics useful to designers are:probability of survival, FIT along lifetime, maximum FIT, and time to cumulative% failed. These metrics are calculated using the series system model. Lognormaldistribution is not self-reproducing for a series system and the proposed metrics donot require any assumption on the system’s failure distribution. The proposed metricssuccessfully identify the impact of individual unit on full-chip reliability. Moreover,a designer has the flexibility to choose any particular metric as the figure of meritdepending on the chip’s application.6970Chapter 4Electromigration ReliabilityComparison of Aluminum andCopper InterconnectsUnder similar test conditions, electromigration reliability of Al and Cu metallizationinterconnect trees demonstrate significant differences because of the differences in in-terconnect architectural schemes presented in section 1.2. The low critical stress forvoid nucleation at the Cu and inter-level diffusion barrier, such as Si3N4, interfaceleads to asymmetric failure characteristics depending on the via position in a line.Unlike Al technology, a (jL) product filtering algorithm with a classification of sep-arate via-above and via-below treatments is required for Cu interconnect trees. Inthis chapter, electromigration reliabilities of Al and Cu dual-damascene interconnectlines are compared using the best estimates of material parameters and the defaultmodel. Differences in atomic diffusivity mechanisms in Al and Cu metallization tech-nologies are also described. Lifetimes of a straight line interconnect are calculatedusing operating conditions from the ITRS projections for future technology nodes.714.1 Immortality Condition FiltersThe (jL) product thresholds for immortality conditions are already mentioned inearlier chapters. Table 4.1 summarizes reported (jL) products for Al and Cu tech-nologies [44, 45, 47, 11].Table 4.1: Reported (jL) product thresholds for immortality conditions in Al and Cutechnologies.MetallizationtechnologyCritical (jL) product thresholdAl interconnects (jL)sat = 4000 A/cmCu interconnects (jL)crit nuc = 1500 A/cm (jL)crit sat = 3700 A/cm(via-above) (via-below)As seen in the table, Al has the highest (jL) product threshold for immortal-ity. The interconnect architecture allows top and bottom conducting shunt layers todivert electron flow around voids in both M1 and M2 type lines. As a result, thetolerable non-fatal void volume in Al M1 and M2 structures is higher than that inCu interconnects. The asymmetry in void volume for failure in Cu metallizationtechnology accounts for the different (jL) products for the via-above and via-belowtypes of interconnects. As discussed in section 2.2, void volume in via-above typeinterconnect is smallest for an open circuit or resistance failure, and hence the lowest(jL) product for immortality is observed.The International Technology Roadmap for Semiconductors projects maximumcurrent density (jmax), among other interconnect related parameters, for each technol-ogy generation in the future. Using the jmax from the 2003 edition, we computed theimmortality length (length below which an interconnect tree is immortal) in varioustechnology generations as illustrated in table 4.2. As technology scaling progresses,the immortality length is consistently decreasing for both Cu and Al technologies.This suggests more and more interconnects trees will be prone to electromigration fail-ure when stressed at their maximum current densities. Al metallization technologyhas the longest immortality lengths due to the highest (jL) product threshold.72Table 4.2: Immortality length in various technology generations (ITRS 2003) with Aland Cu metallizations.jmax Immortality Length (um)Technology Node MA/cm2 Cu via-above Cu via-below Al90nm 0.5 30.0 74.0 80.065nm 1.0 15.0 37.0 40.045nm 3.0 5.0 12.3 13.332nm 4.3 3.49 8.60 9.3022nm 5.8 2.59 6.38 6.904.2 Diffusivity Mechanisms and ModelsThe electromigration-induced diffusion of metallic atoms in an interconnect can oc-cur through different pathways. Due to the differences in architecture schemes andmaterial properties, diffusion pathways and values are significantly different for Aland Cu metallization technologies.4.2.1 Diffusion in Aluminum InterconnectsThe dominant diffusion paths in Al interconnects can be represented by equation 4.1following the convention presented by Hu et al. [58](DZ∗)eff = DSZ∗SδS(2h)+DGBZ∗GBδGBd(1− dw)(4.1)Here, D is the diffusivity, which bears an Arrhenius or exponential form, Z∗ is theeffective charge, δ is the diffusion interface width, and d, h, and w, are the grain size,line thickness, and line width, respectively. Subscript S denotes the Al/refractorymetal liner interfaces at the top and bottom of a line. Subscript GB representsgrain boundary inside a line. The other diffusion pathways, grain bulk and side wallinterfaces, are assumed to have negligible contributions.When line width of an Al interconnect is larger than the Al grain size, for example0.5um, multiple grain boundaries exist in the line as illustrated with a cross-sectionview in figure 4-1(a). Then the dominant diffusion pathways come from the grainboundaries. The microstructure in a wide line, where one of the grain boundary73planes lie in the direction of the current flow, is referred to as polygranular. Suchlines are often termed Al polygranular type. The diffusivity, Dpoly, in Al polygranulartype lines can be expressed asDpoly = Do,GB × e−EaGBkT × δGBd(1− dw)(4.2)where Do,GB is the diffusion coefficient of polygranular type lines, EaGB is the acti-vation energy, k is the Boltzmann’s constant, and T is the temperature.Figure 4-1: Cross-section of an Al interconnect with schematic illustration of diffusionpathways; (a) wide lines are referred to as polygranular type lines where dominantdiffusion paths are grain boundaries (δGB); (b) narrow lines are referred to bambootype lines where dominant diffusion pathways are top and bottom interfaces (δS).Table 4.3 lists the parameter values used in equation 4.2 for calculating diffusivityin Al polygranular type lines [59].Table 4.3: Material parameters used for calculating diffusivity of Al polygranular typelines.Name Symbol ValueDiffusion coefficient Do,GB 1.9× 10−5 m2/sActivation energy EaGB 0.8 eVGrain boundary thickness δGB 0.5 nmGrain size d 0.5 umAs the line width decreases, the microstructure of the line changes from poly-granular to bamboo type where grain boundary planes are normal to the direction ofcurrent flow. In bamboo type Al interconnects, the dominating diffusion pathwaysare the top and bottom interfaces between Al and Ti-based shunt layers as illustrated74in figure 4-1(b). The diffusivity, Dbam, in Al bamboo type lines can be expressed asDbam = Do,S × e−EaSkT × 2δSh(4.3)where Do,S is the diffusion coefficient of bamboo type lines, EaS is the activationenergy, k is the Boltzmann’s constant, T is the temperature, δS is the interface thick-ness, and h is the line height. Diffusivity experiments were carried out by Srikar etal. on 0.4 um thick lines, i.e. href = h = 0.4um [60]. Reported material parametersare listed in table 4.4.Table 4.4: Material parameters used for calculating diffusivity of Al bamboo type lines.Name Symbol ValueDiffusion coefficient Do,S 1.49× 10−4 m2/sActivation energy EaS 0.9 eVInterface thickness-height ratio 2δShref4× 10−54.2.2 Diffusion in Copper InterconnectsIn Cu interconnects, the Cu/Si3N4 interface is the dominant diffusion pathway [40]as illustrated in figure 4-2.Figure 4-2: Cross-section of a Cu interconnect with schematic illustration of diffusionpathway (δS).75The Arrhenius model to calculate diffusivity in Cu isD = Do,S × e−EakT × δSh(4.4)It is important to note that atomic diffusivity has been modelled as independent of Culine width similar to that of Al bamboo type lines. In Cu interconnects, Cu diffusionalong the Cu/Si3N4 interface dominates even for polygranular microstructure [42].The kinetic parameters associated with the effective diffusivity has been deter-mined by Wei et al. through conventional package-level electromigration stress ex-periments using fully-processed dual-damascene Cu interconnects (both via-aboveand via-below structures) under constant current densities [61]. A significant fractionof the test population exhibited steady resistance increase over time prior to failure.This gradual resistance increase results from void growth and the rate of resistanceincrease has been correlated to the drift velocity for electromigration [10]. Amongthe results, the activation energy Ea for Cu electromigration has been determined tobe 0.80± 0.06eV , which is in very close agreement with the value found from lifetimeanalysis for the same structures. With test structure thickness of href = h = 0.24um,Do,SδShrefof equation 4.4 has been determined to be 1.3229 × 10−9m2/s. The mate-rial parameters used for calculating diffusivity in Cu metallization are summarizedin table 4.5.Table 4.5: Material parameters used for calculating diffusivity in Cu metallizationtechnology.Name Symbol ValueDiffusion factor Do,S(δShref)1.3229× 10−9 m2/sActivation energy Ea 0.8 eV4.2.3 Diffusivity ComparisonElectromigration is the electron-flow induced atomic diffusion, and therefore, com-paring the diffusivity of Al and Cu technologies would give us insight on relativeelectromigration reliability. Al metallization has two regions for consideration, bam-76boo and polygranular. For line width less than the grain size (0.5um), we observebamboo region’s diffusivity to be independent of line width. For line width greaterthan the grain size, Al polygranular region’s diffusivity is a function of line widthand is higher than that of bamboo region. Although there is discontinuity in slopeat the point of conversion (line width=0.5um) from bamboo to polygranular region,this composite model is a continuous step model in which polygranular diffusivity ishigher than that of bamboo region. On the other hand, atomic diffusivity in Cu isindependent of line width and is smaller than Al polygranular diffusivity. We havecompared atomic diffusivity for Al and Cumetallization technologies taking a straightinterconnect line in TSMC 0.18um technology with height h = 0.51um. Figure 4-3shows diffusivity versus interconnect line width for Al and Cu technologies at themaximum interconnect temperature T = 105oC as reported in the ITRS.0 0.5 1 1.5 2 2.5 300.511.522.533.5x 10−19 Diffusivity as a function of line width at T=105oCw (um)D (m2 /s)CuAl bambooAl polygranularFigure 4-3: A composite model of atomic diffusivity versus interconnect line width.Figure 4-4 shows a plot of diffusivity versus temperature for different metallizationtechnologies. The interconnect line width is assumed to be 1.0um, twice the grainsize, while calculating Al polygranular diffusivity. As seen in the plot, Al polygranulartype line has the highest diffusivity. Comparing Al and Cu diffusivities, for a givenline width, Cu diffusivity is always about 1/15 of that for polygranular Al, due to the77similarity in activation energies. Al bamboo diffusivity is lower than that of Cu onlyfor temperatures lower than 302oC, because the activation energy in Cu diffusivity islower than that in Al bamboo diffusivity.50 100 150 200 250 300 350 40010−2310−2210−2110−2010−1910−1810−1710−1610−1510−14Diffusivity as a function of temperaturetemperature (oC)D (m2 /s)CuAl bambooAl polygranular, w=2xdFigure 4-4: Atomic diffusivity of Al and Cu metallization technologies at differenttemperatures.During the introduction of Cu metallization, Cu interconnects were assumed to begreater electromigration resistive [62]. Lower atomic diffusivity in Cu might have ledto such perception. However, figure 4-4 shows that Cu diffusivity is only significantlylower than that of Al polygranular type lines; the difference is not significant whencompared to Al bamboo type lines. Therefore, a detailed analysis of lifetimes indifferent technologies is required to quantify relative electromigration reliability.4.3 Lifetime Comparison of Straight Line Inter-connectsA default model that is applicable to both Cu and Al metallization to predict electro-migration lifetime has been discussed in section 2.5. The model estimates the lifetime78of a via considering current densities and diffusivity of connected segments. For astraight line via-to-via interconnect, the equations for time-to-failure due to void nu-cleation, extrusion, and time to void growth to length Lv at any of the two vias arestated below.tnucl =σnuclΩρeZ∗√π4√kTBΩ√DDj2(4.5)textru =σextruΩρeZ∗√π4√kTBΩ√DDj2(4.6)tgrow =LvkTρeZ∗1Dj(4.7)where D is the atomic diffusivity in the straight line and j is the current density.Current density j is fixed at 0.5 MA/cm2 for this analysis. Diffusivity, D, values forCu, Al polygranular, and Al bamboo types are calculated as described in section 4.2.3.Table 4.6 lists the other parameter values used to estimate the time to void nucleationand time to void growth in Cu and Al metallization technologies.Table 4.6: Technology-specific parameter description and values for lifetime calcula-tion.Name Symbol Cu AlStress for void nucleation σnucl 40 MPa 500 MPaEffective charge number Z∗ 1 4.3Bulk modulus B 28 GPa 50 GPaAtomic volume Ω 1.18× 10−29 m−3 1.66× 10−29 m−3Electrical resistivity ρ 1.95 Ωµ− cm 2.67 Ωµ− cmVoid length Lv 0.2 um 0.2 umStraight line interconnect’s lifetimes associated with Cu via-above, Cu via-below,Al polygranular, and Al bamboo types are calculated from tnucl, tgrow, and textru usingthe algorithms in 2.5. Figure 4-5 plots the lifetimes versus temperature for each typeof interconnects.An Al polygranular type line (using width=1um) has the lowest lifetime. Via-above type Cu interconnect has better lifetime than Al polygranular. Via-belowtype Cu and Al bamboo type lines compete for the best lifetime depending on the7950 100 150 200 250 300 350 40010−510−410−310−210−1100101102103104105Interconnect lifetime as a function of temperature with j=0.5 MA/cm2temperature (oC)time−to−failure (years)Cu via−above lifetime (tnucl)Cu via−below lifetime (tnucl+tgrow)Al bamboo lifetime (tnucl+tgrow)Al polygranular lifetime (tnucl+tgrow), w=2xdCross−over temperature, Tc Figure 4-5: Interconnect lifetimes of various types of lines in Cu and Al metallizationtechnologies.0.5 1 1.5 28090100110120130140150160170Cross−over temperature versus current densityj (MA/cm2)Cross−over temperature, Tc (o C)Figure 4-6: Cross-over temperature, defined as the temperature after which a via-below type Cu line has better lifetime than an Al bamboo line, as a function of currentdensity.80temperature. An Al bamboo type line has better lifetime than via-below type Cuinterconnect for temperatures less than 161oC. Defining this particular temperaturepoint to be the cross-over temperature, Tc, after which via-below Cu has the bestlifetime of all, we observe a decrease in Tc with increasing current density as illustratedin figure 4-6.We have defined a typical operating condition of interconnects to be current den-sities below 0.5 MA/cm2 (j ≤ 0.5MA/cm2) and temperature range below 105oC(T ≤ 105oC). Figure 4-7 shows the lifetimes of various types of interconnect lines op-erating at the above condition. Al bamboo type lines have the best lifetime followedby Cu via-below, Cu via-above, and Al polygranular type lines.70 75 80 85 90 95 100 1050 500 10001500200025003000350040004500Interconnect lifetime as a function of temperature with j=0.5 MA/cm2temperature (oC)time−to−failure (years)Cu via−above lifetime (tnucl)Cu via−below lifetime (tnucl+tgrow)Al bamboo lifetime (tnucl+tgrow)Al polygranular lifetime (tnucl+tgrow), w=2xdFigure 4-7: Interconnect lifetimes of various types of lines in Cu and Al metallizationtechnologies in typical operating condition (j ≤ 0.5MA/cm2 and T ≤ 105oC).4.4 Reliability Prediction Using the ITRSThe characteristics of cross-over temperature can be applied to assess interconnectreliability direction in future technology generations. As the maximum current den-sity increases in successive technology generations, according to figure 4-6, decreasing81Table 4.7: Worst case interconnect lifetimes of various types of Cu and Al lines.Technology generation data is from the ITRS 2003 edition [2].Tech. jmax max lifetime of Cu (years) lifetime of Al (years)Node MA/cm2 T (oC) via-above via-below bamboo polygran.90nm 0.5 105 16.19 137.58 223.43 5.1265nm 1.0 105 4.05 64.74 70.6 1.6245nm 3.0 105 0.45 20.68 14.40 0.3332nm 4.3 105 0.22 14.33 9.08 0.2122nm 5.8 105 0.12 10.58 6.31 0.14cross-over temperature indicates better lifetime for Cu via-below type lines. Table 4.7lists the lifetimes of various types of interconnect lines in Al and Cu metallizationsusing reported maximum current density and operating temperature values from theITRS 2003 edition [2]. Al polygranular type or wide Al lines have the worst life-times in almost all technology generations. In the 90 and 65 technology nodes, Albamboo type or narrow Al lines have the best lifetimes. Via-below type Cu lineeventually emerges as the longest lifetime interconnect as current density increases inlater technology nodes. Table 4.7 also points out that Cu interconnects, particularlywith dual-damascene process with Si3N4 capping layer, are as susceptible to elec-tromigration failure as Al interconnects considering the small differences in relativelifetimes.4.5 SummaryThe differences in interconnect architecture between Al and Cu metallization tech-nologies lead to different electromigration failure mechanisms. Unlike Al technology,a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Different diffusivity mecha-nisms also lead to the differences in electromigration lifetimes. Al lines wider thanthe grain size (d = 0.5um) have polygranular microstructure with the highest atomicdiffusivity. On the other hand, narrow Al lines with bamboo type microstructure havelower diffusivity comparable to that of Cu metallization. Diffusivity in Cu technology82is dominant at the Cu/Si3N4 interface and is modelled as independent of line width.Using the best estimates of material parameters and the default model, electro-migration lifetimes of a via-to-via straight line interconnect are compared for fourconfigurations: Cu via-above, Cu via-below, Al bamboo, and Al polygranular. Intypical operating condition (j ≤ 0.5MA/cm2 and T ≤ 105oC), an Al bamboo typeline has the longest time-to-failure followed by Cu via-below, Cu via-above, and Alpolygranular type line. As the maximum current density in interconnect lines in-creases in future technology generations according to the ITRS projections, a Cuvia-below type line emerges as the longest lifetime interconnect. However, the smalldifference in relative lifetimes of Cu and Al technologies suggest that Cumetallizationis as susceptible to electromigration failure as Al. Moreover, the significant differ-ences in failure characteristics outdates traditional techniques and tools for reliabilityanalysis with Al interconnects. A new sophisticated Reliability CAD tool is essentialfor circuit level reliability analysis of Cu interconnects.8384Chapter 5SysRel: Circuit-Level ReliabilityCAD ToolSysRel is a new reliability CAD tool for electromigration reliability analysis and com-parison with Al and Cu metallization technologies in 2D and 3D circuit layouts.SysRel utilizes the interconnect tree based hierarchical reliability analysis. The soft-ware design approach in SysRel is detailed in this chapter. The chapter also containsreferences to source code files wherever appropriate. The earlier sections present gen-eral algorithms and data-structures for layout parsing and extracting interconnecttrees. Then the graphical user interface and reliability analysis flow in SysRel arediscussed. SysRel utilizes a set of joint stochastic reliability metrics based on thedesired lifetime of a chip and combines reliability figures from individual fundamen-tal reliability units. Simulation results with a 32-bit comparator circuit layout arediscussed to demonstrate the functionality and significance of the tool.5.1 Software ArchitectureSysRel is written in Java for the Java 2 platform. The Java platform consists of threecomponents; Java Language, Java Virtual Machine (JVM), and Java ApplicationProgram Interface (API). Java Language defines the semantics and syntax of writinga program. JVM executes Java byte codes produced by compiling a Java program.85The Java API is a set of predefined classes and methods1 provided with the JavaDevelopment Environment. The Java API includes everything from data-structureclasses, such as Vector, ArrayList, and Hashtable, to Graphical User Interface (GUI)development classes. SysRel makes extensive use of the APIs from Java DevelopmentKit version 1.3.1 [63]. SysRel consists of 32 classes which can be grouped into thefollowing six categories.• Main application classes• Graphical interface classes• File parser classes• Corner-stitched data-structure classes• Layout and tree representation classes• Core reliability engineAppendix A defines each category listed above and briefly describes the majorclasses in them. The code length of SysRel is approximately 9000 lines.5.2 Graphical User InterfaceSysRel is a stand-alone application with its own desktop. The GUI is developedusing the Java Swing2 package. Figure 5-1 shows the graphical interface with alayout opened in the Layout Window. Menu items invoke selected operations inSysRel and reports outcome in the Output Window. Table 5.1 lists the menu barsand corresponding operations through available menu items.1Functions defined inside classes for specific operations, such as construction of the class anddata-manipulation.2Swing is the new package in Java 2 with GUI control classes such as window frames, dialogboxes, menu items, check boxes, and buttons.86Figure 5-1: Screen shot of SysRel’s desktop pane. Menu items and options are de-scribed in table 5.1. At the top right corner are selection tabs to enable thermalanalysis and select either Cu or Al metallization. Inside the desktop pane, there areOutput Window, Layout Window, Plot Window, and Tree Rank Table.87Table 5.1: Menu bars and corresponding operations in SysRel.Menu Menu ItemsFile Open Magic layout file, Read EM parameters(.emparam) file, ExitThermo-file Read Hierarchical Magic file, Read Power Distri-bution (.cpower) file, Write Power Density Ma-trix (currentpden.m) file, Read Temperature Pro-file Matrix (tprofile.dat) fileElectromigration List EM parameters, Update selected EM param-eters, Extract Failure Units, Apply JmaxL Filter,Compute local jL, Apply jlocalL filter, Apply De-fault ModelNon-blocking ViaAnalysisList via types, Assign non-blocking vias, MergetreesReliability Budget Read Cell Reliability Characterization, Full ChipMetric, Plot % failure, Rank Failure UnitsHelp Documentation, About5.3 Circuit Layout ParsingSysRel reads layout files in Magic format, referred to as .mag files, created with Magicand 3D-Magic. A .mag file provides an ASCII file representation of a circuit layoutwith coordinates of rectangular tiles representing mask layers [37]. A set of coordi-nates has a header tag << layer >>, where “layer” defines the mask type of followingrectangles. Table 5.2 shows a sample .mag file. While parsing such a file, SysRel de-composes rectangular elements into mask layers and their positions (source code:ParseMAGFile.java). The mask information is stored in a data-structure known ascorner-stitching introduced in Magic [64]. According to the corner-stitching data-structure, multiple planes, such as active, oxide, poly, and metal1, are superimposedon each other to represent a layout. Each plane contains different types of non-overlapping rectangular tiles with stitches at the four corners. Figure 5-2 illustratesa representation of three corner-stitched solid tiles in a single plane.The Java source files defining the corner-stitching data-structure in SysRel arePlane.java, PlaneType.java, Tile.java, and TileType.java. Layout.java implementsthe class that puts together multiple Tile and Plane objects to provide an internal88Table 5.2: A sample .mag layout file.magictech scmostimestamp 962374816<< polysilicon >>rect -21 -4 -12 -1rect -8 -4 10 -1<< metal1 >>rect -27 35 -21 36rect 8 35 20 50<< polycontact >>rect -12 -4 -8 0<< labels >>rlabel polysilicon -1 -3 -1 -3 1 oparlabel metal1 -10 2 -10 2 1 m1th<< end >>Figure 5-2: Corner-stitched representation of a single plane with multiple tiles in aMagic layout. The gray areas are solid tiles that are corner-stitched to neighboringspace tiles.89representation of a layout. While plotting the layout on a window, the Planes areaccessed in a serial fashion, and the corner-stitched Tiles in each Plane are paintedusing an appropriate color (source code: LayoutPanel.java).A .mag file only provides the coordinates of mask layers in a layout. Therefore,further information on the connectivity and type of mask layers is retrieved fromthe technology file, scmos3D.tech27. While parsing a .mag file, the tiles that alsorepresent contacts and inter-wafer vias are specially tagged. A contact tile has mul-tiple representations, one at every plane that it connects. For example, m2contactconnects metal interconnects from metal1 and metal2 planes, and has one tile rep-resentation at the metal1 plane and another at the metal2 plane. The Java sourcefile, TechDB.java, parses the technology file to retrieve such crucial connectivity in-formation for contacts. It also identifies the inter-wafer vias specific to 3D integrationtechnology.5.4 Interconnect Tree ExtractionThe corner-stitching data-structure enables several key operations of a CAD layouttool in a very efficient manner. Two critical operations are locating a tile in a givenarea and searching for its neighboring tiles in a plane. Both operations are at theheart of extracting interconnect geometries from a layout. Given a particular tile, alladjacent tiles are retrieved from the corner-stitches implemented as an ArrayList3.The adjacent tiles are then stored in a Vector4 (source code: ITree.java) [63]. Using adepth-first search algorithm, the top left-most tile is identified, and the whole tree isbuilt via a depth-first walk on adjacent tiles [46]. Figure 5-3 illustrates an interconnecttree extraction from corner-stitched representation of tiles.Setting the top left-most tile as a starting point facilitates the computation ofseveral useful interconnect parameters including via-to-via paths in an interconnecttree. SysRel calculates the length of all possible via-to-via paths using the coordinates3The ArrayList class in Java implements a resizable array.4The Vector class is similar to ArrayList except that this implementation is synchronized in caseof simultaneous element accesses.90Figure 5-3: Extraction of an interconnect tree from corner-stitched representation oftiles. Tiles marked with a cross are contact tiles and are the starting and terminatingpoints for this particular tree.of rectangular tiles. Moreover, the parameters are calculated at the same time when atree is being built with the depth-first walk algorithm. An ITree object, the internalrepresentation of an interconnect tree, stores the parameters in a path-table for futureuses. For the interconnect tree shown in figure 5-3, the path-table contains data fortwo paths, starting at the top left-most contact tile and ending at the two terminatingcontact tiles.5.5 Reliability Analysis FlowThe reliability analysis flow diagram in SysRel is based on the hierarchical reliabil-ity analysis approach discussed in sections 2.3 and 2.4 for Cu and Al metallizations,respectively. Figure 5-4 shows the flow diagram for reliability analysis in SysRel. Inaddition to a layout file in Magic format, SysRel requires input for process parametersand critical stress numbers for use in the default model. Current estimates in inter-connects trees are based on simulation results from commercial power analysis tools,such as Spice or PowerMill. While Vdd and Gnd lines are stressed at DC currentscomputed from total average power dissipation of the circuit, current flow in signalnetworks are assigned from average cell power dissipations. This gives conservativecurrent estimates in the interconnect trees. Detail current flow information includingcurrent directions in different segments of an interconnect tree is not available from91any power analysis tool, and more importantly, associated computation is often notfeasible in a large circuit layout. The electromigration parameters, .emparam, file de-fines necessary parameters for immortality filtering thresholds, metallization specificparameters in the default model, and power dissipation in the circuit.tuoyaL cigaMseerT-I tcartxE r-I trtsaiV yfissalCxamL etupmoCsi yfisslx t)Lj( ylppA xam retlifevoba-aiv :uC)Lj( :lA tirc)j( l xa rtlif-i :)j( :l tirc?ssaP ssxamL?evoba-aiv -ilatrommIseyon woleb-aiv ylppAretlif l-i lrtlif?ssaPseyon evoba-aiv dniFav_xamL & edon v-iv ix evoba-aiv ylppAretlif v-iv ylrtlif?ssaP sslatrommIsey ononj etamitsE ij tit i)Lj( ylppA ffe retliF)j( yl ffe rtli?ssaP sslatrommIseyon tluafeD ylppAledoM tlf ll noitalumiSmiSmE/uC htiw itlii/ ti pihC lluFledoM ytilibaileR i lll tiliil ytilibaileRtegduBseywolf lA ot elbacilppa ton spetSFigure 5-4: Reliability analysis flow diagram in SysRel. The steps boxed in dashedrectangles apply only to reliability analysis in Cu metallization technology.SysRel is a GUI based interactive tool requiring user input before initiating aprocess in the flow diagram. A technology selection tab allows a user to choose ei-ther Cu or Al metallization technology for current analysis. A user can select allor any particular metallization layer in a layout for tree extraction. Extracted treesare high-lighted along a display of statistics. While a single (jL) product thresholdis used for the immortality condition in Al metallization technology, via-based im-mortality filtering with separate treatments for via-above and via-below types in Cumetallization requires extra steps as marked in the flow diagram. After each filter-ing stages, the immortal trees are highlighted in green and discarded from further92analysis. The maximum current density, jmax is read from the emparam file. Localcurrent density jlocal is conservatively calculated using current flow estimation fromaverage cell power dissipations. As mentioned earlier, segment-based current densityvalues and directions5 are unavailable. The worse case reliability occurs when cur-rents from all connected segments are flowing into a via-above junction and flowingout of a via-below junction in Cu metallization, and either flowing into or out of aW -filled via junction in Al metallization [10]. We conservatively assume the worstcase current directions during the (jL)eff filtering stage and time-to-failure calcula-tions. Time-to-failures (t50) of mortal trees are computed using the default modeldiscussed in section 2.5. Finally, times-to-failure from different trees are combinedusing a joint stochastic process of series elements of lognormal lifetime distributionwith standard deviation (σ) as reported in experimental work. Given a target lifetimeof the chip, the full-chip reliability metrics for output are probability of no failure,maximum failure rate in FIT, and time to any cumulative % failure.As illustrated in figure 5-4, there exists a link to MIT-Emsim or Cu-Emsim whichis in parallel to full-chip reliability analysis. MIT-Emsim and Cu-Emsim are mi-crostructure level electromigration simulators currently under development [50, 51].Microstructure level simulations involve detail numerical analysis. Although mi-crostructure level simulations are computation intensive, a more accurate estimateof stress evolution with various current directions in interconnect trees and electro-migration lifetimes are derived using such simulations. Only the least reliable trees,as indicated by SysRel, would be passed to MIT-Emsim or Cu-Emsim.5.6 Simulation with 32-bit Comparator LayoutA 32-bit comparator circuit layout is used to verify functionality and accuracy of thereliability flow in SysRel. The 32-bit unsigned integer comparator is designed usinga design flow from behavioral description with VHDL to physical layout. The toolsused in the flow are Design Analyzer (analysis and synthesis tool), Silicon Ensemble5All signal networks, except for Vdd, Gnd, and clock, carry bidirectional currents.93(place and route tool), and Magic (layout editor). An IIT standard cell library forTSMC 0.18um process is used for synthesis [65]. Total dynamic power reported inDesign Analyzer using the library cell characterization data is 26.6mW at V dd = 5V .It is also possible to use a circuit simulator, such as HSpice, for estimating powerdissipation. For this reliability analysis, we used the power dissipation as calculated byDesign Analyzer. The layout has up to five layers of metallization; metal1 and metal2for intra-cell routing, and all metal layers for inter-cell routing. Power delivery linesare in metal1 and metal2 in a ring format (figure 5-5). The layout size is approximatelyPower Delivery RingFigure 5-5: The 32-bit comparator circuit layout analysis in SysRel. Eight mortaltrees come from the power delivery rings as marked in the layout.164um × 164um. According to the ITRS, a jmax value of 0.96 MA/cm2 and worstcase interconnect temperature of 105oC are used. While the signal lines in the designare stressed with bidirectional currents, the Vdd and Gnd lines have the worst caseunidirectional current density of 0.42 MA/cm2.945.6.1 Copper Metallization TechnologyTable 5.3 shows the results of hierarchical reliability analysis with Cu metallizationtechnology in the 32-bit comparator circuit layout. After applying the first immortal-ity filtering with via-based jmaxL thresholds, 1023 out of 1143 trees are found to beimmortal. The second filtering step using the tree’s jlocalL products finds 112 moretrees to be immortal. Figure 5-5 shows the layout after the final simulation stepwhen the mortal trees are marked. According to the analysis, only eight interconnecttrees in Vdd and Gnd lines in the power delivery rings are prone to electromigrationfailure. Four metal1 trees are via-above type with lifetimes of 23.2 years. The otherfour trees are metal2 via-below type lines with lifetimes of 168.7 years. The resultingfull-chip reliability metrics are shown in step 5 of table 5.3.Table 5.3: SysRel simulation results of hierarchical reliability analysis with Cu met-allization in the 32-bit comparator circuit layout.Step 1 Layout Extraction (total # of interconnect trees=1143)Metal Plane # of interconnectsmetal1 580metal2 438metal3 102metal4 20metal5 3Step 2 Via-based (jmaxL) filterNumber of immortaltrees identified1023Step 3 Via-based (jlocalL) filterNumber of immortal trees identified 112Step 4 Default Model (with σnucl = 40MPa) on 8 mortal treest50 of 4 mortal tees in metal1 (via-above) 23.2 yearst50 of 4 mortal tees in metal2 (via-below) 168.7 yearsStep 5 Full chip stochastic analysis (σ = 0.81, lognormal)Target chip lifetime 10 yearsProbability of no failure 0.524max FIT 15.4k 10th yeart50 for full chip 10.35 years955.6.2 Aluminum Metallization TechnologyTable 5.4 shows the results of hierarchical reliability analysis with Al metallizationtechnology in the 32-bit comparator circuit layout. After applying the first immortal-ity filtering with a single (jL) product threshold, 1093 out of 1143 trees are identifiedas immortal. The second filtering step using the tree’s jlocalL products finds 42 moretrees to be immortal. The default model is applied to the same eight mortal treesin power delivery lines shown in figure 5-5. As no via-classification is required inAl technology, all the trees have lifetimes of 4.39 years. The lifetimes are very lowas the 2.5um wide lines, wider than an Al grain size of 0.5um, have Al polygranu-lar microstructure. The full-chip metrics are significantly lower than those from Cumetallization analysis.Table 5.4: SysRel simulation results of hierarchical reliability analysis with Al metal-lization in the 32-bit comparator circuit layout.Step 1 Layout Extraction (total # of interconnect trees=1143)Step 2 (jmaxL) filterNumber of immortaltrees identified1093Step 3 (jlocalL) filterNumber of immortal trees identified 42Step 4 Default Model (with σnucl = 500MPa) on 8 mortal treest50 of mortal tees 4.39 yearsStep 5 Full chip stochastic analysis (σ = 0.81, lognormal)Target chip lifetime 10 yearsProbability of no failure 3.309× 10−7max FIT 205kt50 for full chip 1.43 years5.7 Implications of SysRelReliability simulations with the 32-bit comparator layout clearly demonstrate thebasic functionality of SysRel. More importantly, SysRel identifies electromigrationcritical (mortal) trees and allows a designer to focus on those trees while ignoringnumerous other immortal trees. “What-if” analysis is possible on selected mortal96trees to observe the impact on full-chip reliability. In reliability simulation with Cumetallization in the comparator circuit layout, the worst lifetimes of 23.2 years infour mortal trees are due to via-above type Cu line in metal1. Increasing only thoseline widths from 2.5um to 5um and running the reliability simulation again, SysRelpredicts lifetime improvement in the worst case lines from 23.2 years to 92.9 yearsand the new full-chip reliability metrics are t50 = 37.5 years, FIT 563, and probabilityof survival=0.98.In reliability simulation with Al metallization, all eight mortal trees are Al poly-granular type lines due to their 2.5um widths. As discussed in section 4.3, narrowAl lines (width ≤ grain size=0.5um) have bamboo type microstructure and higherelectromigration lifetimes due to lower diffusivity. Using a track layout method withnarrow (0.5um) metal lines, as illustrated in figure 5-6, we can convert the mortallines in the power supply rings from polygranular type to bamboo type. Using such atechnique, the lifetime of each metal line can be improved to 306.82 years and the newfull-chip reliability metrics are t50 = 99.8 years, FIT 5.9, probability of survival= 0.99.2.5um0.5umPolygranular AlBamboo Al3.7umFigure 5-6: Layout technique for Al polygranular to bamboo type conversion in aninterconnect line. Let current through the interconnect line is I A. Then currentdensities, jpolygranular = I/(2.5 × h), jbamboo = (I/5)/((2.5/5) × h) = I/(2.5 × h).Current density remains the same in this conversion. We can treat the bamboo Altrack line as a single tree.5.8 Three-Dimensional IC Analysis in SysRelA 3D 32-bit comparator circuit is laid out from the 2D version using data-path foldingtechnique. The 2D circuit is first synthesized with four rows of cells. Then the data-path is folded to create two wafers in the 3D circuit such that each wafer contains97two rows. 3D-Magic is used to place inter-wafer vias and power delivery rings in eachwafer. The layout sizes corresponding to top and bottom wafers are 141.6um×75.5umand 141.6um× 79.7um. Figure 5-7 shows the layout view in SysRel.Table 5.5 lists the reliability simulation results of the 3D 32-bit comparator layoutwith Cu metallization technology. Out of 1115 trees from two wafers, a total of eighttrees, four from each wafer, are mortal as marked in figure 5-7. The mortal treesare in metal1 in the power delivery rings. The default model predicts lifetimes ofeach tree to be 92.97 years. The full-chip reliability metrics as shown in the table arebetter than those of the 2D layout. As total power dissipation is distributed in twowafers in the 3D circuit, current densities in the mortal lines are approximately scaledby half. In 2D layout, metal2 lines in the power delivery rings were mortal. However,due to data-path folding, those metal2 lines in the 3D circuit layout have lower Lmaxand get filtered out. Thus the 3D circuit demonstrates reliability improvement dueto wire length reduction and power distribution in two wafers.Table 5.5: SysRel simulation results of hierarchical reliability analysis with Cu met-allization in the 3D 32-bit comparator circuit layout.Step 1-3 Layout Extraction (total # of interconnect trees=1115,# of mortal trees=8)Step 4 Default Model (with σnucl = 40MPa) on 8 mortal treest50 of mortal trees 92.97 yearsStep 5 Full chip stochastic analysis (σ = 0.81, lognormal)Target chip lifetime 10 yearsProbability of no failure 0.976max FIT 1020t50 for full chip 30 yearsDuring the reliability simulation of the 3D circuit, a worst case interconnect tem-perature of 105oC, as reported by the ITRS, was used for both wafers. Temperaturein 3D circuits are expected to be higher than that in 2D circuits due to higher powerdensity in a smaller foot-print [30]. Electromigration lifetime is exponentially depen-dent on temperature. Therefore, reliability improvement illustrated in this analysis isnot necessarily conclusive and is highly dependent on thermal management techniquesused in the 3D circuit. In addition, reliability of inter-wafer vias in the presence of98Figure 5-7: The 3D 32-bit comparator circuit layout for SysRel reliability simulation.Mortal trees in each wafer are marked in the layout.99bonded interface are under active study. No lifetime models for inter-wafer vias areyet available for application to SysRel.5.9 SummaryA new reliability CAD tool, SysRel, has been developed for circuit-level electromi-gration analysis with either Cu or Al metallization technology in conventional and3D circuits. SysRel is written on the Java 2 platform. SysRel is an interactivegraphical user interface based RCAD tool that treats circuit layouts from Magic and3D-Magic. The basic reliability analysis in SysRel is based on hierarchical reliabilityanalysis with interconnect trees as the fundamental reliability units. Based on thedifferences in electromigration failure mechanisms observed in experimental work, wepresent a (jL) product filtering algorithm with a classification of separate via-aboveand via-below treatments in Cu metallization. After the filtering of immortal trees,a default model is applied to the remaining trees to compute reliability figures for in-dividual units. SysRel utilizes new reliability metrics based on the desired lifetime ofa chip and combines reliability figures from individual fundamental reliability units.A 32-bit comparator circuit layout in 2D and 3D technology is analyzed in SysRelto demonstrate its functionality and significance. SysRel identifies electromigrationcritical (mortal) trees and allows a designer to focus on those trees while ignoringnumerous other immortal trees. “What-if” analysis is possible on selected mortaltrees to investigate the impact on full-chip reliability.100Chapter 6Cell-Based Reliability Analysis inSysRelLarge digital circuits, such as microprocessors and application specific ICs (ASICs),are often designed and laid out using a hierarchical scheme with blocks or modules.The hierarchy is crucial in managing the design complexity as well as facilitatingparallel design efforts in the design team. Each block or module is thus designed andlaid out taking the requirements into account from neighboring blocks and overallproduct specification. Characterization for power and timing are often done block-by-block before the full-chip is integrated. To integrate electromigration analysis intosuch an IC design flow, we have introduced the concept of cell-based reliability analysisin SysRel. According to this concept, each cell or module layout is characterized forelectromigration reliability using SysRel. When a large cell-based layout is analyzedthat uses pre-characterized cells, SysRel reuses reliability results of those particularcells.Cell-based reliability analysis is ideal for integrating electromigration analysis intoa conventional IC design flow. A block or module can be characterized for reliabilitywhile it is characterized for power and timing. Moreover, reusing cell characterizationdata reduces computational load while analyzing a very large circuit. Treating alarge flattened layout, such as that of a microprocessor, is impractical in most CADtools. Block level abstraction is already in use to manage the computation load101of CAD applications. This chapter outlines the infrastructure in SysRel for cell-based electromigration reliability analysis. The accuracy and advantages of cell-basedanalysis with SysRel are demonstrated using adder and comparator circuits.6.1 Cell Characterization in SysRelAccording to the cell-based reliability analysis, first, a cell or module layout is ana-lyzed for electromigration reliability using SysRel. The output is formatted to recordthe number of mortal units in the cell and corresponding lifetimes. The outputs fromeach cell are stored in a cell characterization file, sysrelcell.char file, in a format shownin table 6.1.Table 6.1: Cell reliability characterization data format in sysrelcell.char file# example cell data for immortal cellCellname xor2x1Number-of-mortal-FRU 0# example cell data for mortal cell with 4 FRUsCellname or2x1Number-of-mortal-FRU 4 20 21 22.3 54 yearsA standard cell library developed at Illinois Institute of Technology (IIT) with 27basic cells, such as nand, nor, inv, and aoi gates, is used in this work to synthesizecell-based circuit layouts [65]. All the cells have been characterized using SysRelto create the sysrelcell.char file. Due to short line length in cell layouts (maximumcell size is approximately 13um × 4um), all the cells are immortal after the (jmaxL)product filter with both Al and Cu metallizations. Figure 6-1 shows immortalityafter (jmaxL) product filter in the largest cell, FAX11, in the cell library.1FAX1 implements a binary adder with Y C = ((A&B)|(B&C)|(C&A)) and Y S = (A⊕B ⊕ C)with inputs A, B, and C.102Figure 6-1: The largest cell, FAX1, characterization with SysRel. All trees highlightedin green indicates immortality after the (jmaxL) product filter.6.2 Hierarchical Layout Support in SysRelA hierarchical Magic layout file instantiates different types of cells in the layout withreferences to separate layout files corresponding to those cells. SysRel identifies cellinstantiations in a hierarchical root layout, and then reads the corresponding layoutfile. In the case of multiple instantiations of the same cell, cell layout is read onlyonce. SysRel Output Window lists the statistics on the types and number of cellsused in a layout. The hierarchy levels are preserved after reading the root layout. Thenumber of levels is shown in the “Hierarchy” menu of the Layout Window. Figure 6-2shows a cell-based layout with three levels of hierarchy.Using the radio buttons in the “Cell View” menu, users can select any particularhierarchy level for display. The flat root level displays the metal layers from cells inall levels as shown in figure 6-2. When any particular level is selected via a radiobutton, all lower levels including the selected one get hidden in the layout window.Hidden cells are outlined and their instance names appear at the center.While extracting interconnect trees from a hierarchical layout, SysRel extractstrees only from the metal layers that are visible in the Layout Window. Thus, ex-tracting trees at the flat root level would extract trees from metal layers in all cellsincluding the topmost level. If the cells are already characterized for reliability, a user103RootLevel 2Level 3Figure 6-2: Hierarchical layout view in SysRel.can exclude those from tree extraction by selecting their hierarchy level. In that case,interconnect trees are extracted from higher levels and fed into the basic reliabilityanalysis flow diagram described in section 5.5. After the lifetimes of mortal treesare computed, SysRel reads the cell characterization file to include lifetimes for anymortal units in the hidden cells. The “Read Cell Characterization (.cellparam) file...”menu item in the “Reliability Budget” menu invokes a file chooser dialog box to selectthe .cellparam file. The full-chip reliability is computed using a series system modelof all mortal units, as described in section 3.4.6.3 Cell-based Reliability SimulationA simple 4-bit adder, synthesized using the IIT cell library, is first used to debugand verify accurate cell-based reliability analysis in SysRel. The adder layout hastwo levels of hierarchy: root level consisting of inter-cell routing and power deliverylines, and level 2 consisting of 18 cells from the library. Figure 6-3 illustrates level2 view of the layout in SysRel. Extracting interconnect trees from this view willextract trees from inter-cell routing and power lines only. Table 6.2 lists the statisticsof interconnect trees and cells in the adder circuit layout.104Extraction levelHidden cell rowsFigure 6-3: Cell-based adder layout’s level 2 view in SysRel.Table 6.2: Statistics of Fundamental Reliability Units in the 4-bit adder layout.Total # of trees in flat layout 317# of trees from inter-cell routing 116% of trees from cells 63.4Total number of cells 18Cell ReportCell name # of instancesnand3x1 1and2x1 1nand2x1 5or2x1 2fill 2xor2x1 7Data in table 6.2 illustrate that 63.4% of the interconnect trees come from cells.Thus the cell-based full-chip reliability analysis is expected to increase computationalefficiency in SysRel. Moreover, the cell report also suggests that only a few types ofcells are used multiple times in the circuit layout. SysRel full-chip reliability analysiswith the 4-bit adder circuit predicts immortality in both cell-based and fully flattenedlayout analyses.Section 5.6 presented SysRel reliability simulations with a fully-flattened 32-bitcomparator circuit layout. The hierarchical version of the same layout is analyzedhere using the cell-based approach. Table 6.3 lists the statistics of interconnect trees105and cells in the comparator circuit layout.Table 6.3: Statistics of Fundamental Reliability Units in the 32-bit comparator circuitlayout.Total # of trees in flat layout 1143# of trees from inter-cell routing 678% of trees from cells 40.7Total number of cells 132Cell ReportCell name # of instancesoai21x1 48aoi21x1 14nand2x1 1invx1 55fill 14Table 6.3 illustrates that 40.7% of the interconnect trees come from cells in thiscircuit. Similar to the adder circuit layout, only few types of cells are used multipletimes in the comparator circuit. SysRel reliability analysis with the 32-bit comparatorcircuit predicts the same eight trees from power delivery lines to be mortal in cell-based analysis with both Al and Cu metallizations. Therefore, the full-chip reliabilityresults are the same as presented in section 5.6.6.4 Computational EfficiencyThe two metrics used to investigate the computational efficiency with cell-based relia-bility analysis are the times required for layout drawing and interconnect tree extrac-tion. Layout drawing in the Layout Window entails painting a collection of rectanglesusing the Java Graphics2D class. Rectangles are drawn in different colors to repre-sent different mask layers. When a cell-based layout is viewed in any hierarchy levelother than root level (figure 6-3), cell layouts are hidden in outlined boxes. Table 6.4lists the time required for layout drawing with the 4-bit adder and 32-bit comparatorcircuit layouts. The layouts are drawn while zoomed to fit the Layout Window ofapproximately 3inch× 3inch. The time recorded is the average time computed usinga few trials.106Table 6.4: Time required for layout drawing in SysRel.4-bit adder circuit 32-bit comparator circuitAnalysis mode time (ms) Analysis mode time (ms)Cell-based 125 Cell-based 563Flattened layout 313 Flattened layout 1250Interconnect trees are extracted from the layout using only the visible tiles in theLayout Window. During a cell-based analysis, interconnect trees inside a cell are notextracted as the cell layouts are just outlined. Table 6.5 lists the time required forextracting interconnect trees in the 4-bit adder and 32-bit comparator circuit layoutsduring different modes of analysis.Table 6.5: Time required for extracting interconnect trees in SysRel.4-bit adder circuit 32-bit comparator circuitAnalysis mode time (ms) Analysis mode time (ms)Cell-based 94 Cell-based 265Flattened layout 172 Flattened layout 485We observe significant reductions in times required for layout drawing and inter-connect tree extraction in tables 6.4 and 6.5, respectively. Table 6.6 summarizes thepercentage improvement using the two metrics to quantify computational efficiencyin cell-based reliability analysis in SysRel.Table 6.6: Computational efficiency with cell-based reliability analysis in SysRel.% improvementLayout drawing tree extraction4-bit adder 60 4532-bit comparator 55 456.5 SummaryLarge circuits are often designed using a hierarchical flow where individual blocks orcells are first designed and characterized. In this chapter, we have introduced cell-levelreliability characterization and computationally efficient full-chip reliability analysis107in SysRel. Cell layouts can be characterized for reliability while they are characterizedfor power and timing. The outcome of reliability characterization is the number ofmortal trees and the lifetimes. An IIT standard cell library has been characterizedusing SysRel to create the reliability characterization file sysrelcell.char. SysRel readsand retains the hierarchy levels in a hierarchical Magic layout. Reliability simulationresults with two hierarchical Magic layouts, a 4-bit adder and 32-bit comparator,demonstrate the proper functionality and significance of cell-based reliability analysisin SysRel.Statistics from the hierarchical layouts suggest that only a few cells are usedmultiple times and a large percentage (minimum 40% found in the 32-bit comparatorlayout) of total extracted interconnect trees are internal to cells. Therefore, cell-basedreliability analysis, where cells are pre-characterized and hidden in a hierarchicallayout, significantly reduces simulation time in SysRel. The two metrics used toinvestigate the computational efficiency with cell-based reliability analysis are thetimes required for layout drawing and interconnect tree extraction. The maximumimprovement in times required for layout drawing and interconnect tree extraction of60% and 45%, respectively, have been demonstrated with the 4-bit adder and 32-bitcomparator layouts. Both cell-based and flattened layout analyses produce the samefull-chip reliability results.108Chapter 7Non-blocking Via Analysis inCopper Metallization TechnologyAn interconnect tree is the fundamental reliability unit for circuit-level reliabilityassessments for metallization schemes with fully-blocking boundaries at the vias. Atree is composed of linked segments in a single layer of metallization, in which metalatoms can freely diffuse and lead to coupled stress evolution in its segments. Becauseof blocking boundaries at vias, stress in a tree is not affected by stress in other trees.The tree-based hierarchical reliability analysis flow described in section 5.5 appliesto circuit-level reliability assessments with fully-blocking vias. In Al metallizationtechnology, tungsten-filled vias always block electromigration. In Cu metallizationtechnology, refractory liners at the bottom of vias generally block electromigration.However, some experimental studies suggest that this is not always the case, and asliner thicknesses are decreased, fully-blocking liners at vias become less certain dueto liner ruptures. When Cu-filled vias are not fully blocking, an interconnect tree isconnected to other metallization layers. While liner ruptures can lead to increasedlifetimes in test structures, the impact of tree linking on circuit-level reliability is notclear. Therefore, we have incorporated in SysRel a capability for making reliabilityanalysis with non-blocking vias in a layout [66].1097.1 Non-blocking Via Due to Liner RupturesCu interconnects are fabricated by the dual-damascene method, in which a trenchis first etched into a blanket layer of dielectric material (usually SiO2) before fillingit with Cu by electroplating. Since Cu undergoes field enhanced diffusion in mostdielectric materials (including SiO2), in order to prevent Cu atoms from diffusinginto the device layer, thin refractory metal layers, referred to as liners, consisting ofTantalum (Ta) or Tantalum Nitride (TaN) are placed at the sides and bottom of theCu line. When vias are filled with Cu, there exists a liner at the bottom of a via.Hu et al. carried out Cu electromigration studies with different liner thicknessesand blocking materials at the cathode and anode ends of the lines [67]. Figure 7-1illustrates three layers of Cumetal interconnects, used in their experiments, connectedby vias V1 and V2. The liner thicknesses at the bottom of a via are 3nm and 10nmfor thin and thick liners, respectively. The study demonstrated that a 3nm thick linercan lead to an increase in mean-time-to-failure by more than an order of magnitude.thin liner(3nm)thick liner(10nm)Figure 7-1: Multi-level Cu interconnects with different liner thicknesses [67].Wei et al. conducted electromigration experiments with straight line via-to-viaCu dual-damascene test structures as shown in figure 7-2 [68]. Few 1000um long linestested at j = 2.0MA/cm2, and 800um long lines tested at j = 2.5MA/cm2 neverfailed even though analytically computed mechanical stress values in the lines werehigh enough for void nucleation. The apparent immortality of a sub-population of110long lines is postulated to be the result of stress-induced ruptures of the Ta linersat the vias. In a test structure in figure 7-2, liner ruptures would allow continuousflow of Cu to and from the lead lines and contact pads, which serve as large sinksand reservoirs for Cu atoms. Therefore, the liner ruptures would cause immortalityin those types of lines.V VI IFigure 7-2: Straight line via-to-via Cu dual-damascene test structure for electromi-gration experiments.7.2 Non-blocking Via Assignment in Circuit Lay-outIn Cumetallization technology, metal1 to poly-silicon gate, diffusion, such as source/drain,substrate, and well contacts are tungsten (W ) filled similar to vias in Al metalliza-tion. Those vias always block electromigration. On the other hand, Cu-filled viasconnecting two metal layers have Ta-based liners at the bottom. Vias with liners mayor may not block electromigration depending on the liner thickness, stress build-up,and other material properties. Therefore, non-blocking via assignment in SysRel isdesigned to be stochastic in nature. Table 7.1 illustrates the input parameters fornon-blocking via analysis defined in sysrel.emparam file.The first line in table 7.1 is “stochastic 90” indicating that 90% of potentially non-blocking vias in the circuit layout will be assigned to be non-blocking. The stochasticvalue needs to be greater than 0% and can be as high as 100%. The 100% value wouldindicate a deterministic assignment of non-blocking boundaries in all metal-to-metal111Table 7.1: Input parameters for non-blocking via analysis defined in sysrel.emparamfile.# Non-blocking via analysis in CuStochastic 90random seed 123412342force blocking 5 polycontact ndcontact pdcontactpsubstratepcontact nsubstratencontactvias in the layout. The second parameter in table 7.1 is a random seed that needsto be a maximum of 9 digit number for the pseudo-random number generator inSysRel. During stochastic non-blocking via assignment, SysRel tags each potentiallynon-blocking via with a random number. The random numbers are sorted, and thena cut-off value is picked from the sorted list that would assign the desired percentageof vias to be non-blocking. The same random seed value during multiple SysRelsessions will assign the same set of vias in a circuit layout to be non-blocking. Thefinal parameter for non-blocking via analysis allows a user to list a set of vias to betreated as fully blocking. The entry in table 7.1 lists five W -filled gate, source/drain,and substrate contacts that need to be treated as fully blocking in Cu metallizationtechnology. A user can also list any particular metal-to-metal vias, such as metal2to metal3 via, to be fully-blocking. Such flexibility would allow a user to selectivelyinvestigate the impact of non-blocking boundaries at different metal-to-metal vias.7.3 Steps for Non-blocking Via Analysis in SysRelThe “Non-Blocking Via Analysis” menu bar in SysRel provides three menu items forthe core operations in non-blocking via analysis (figure 7-3). The “List via types”menu item displays the number and types of vias used in the circuit layout. The“Assign Non-blocking Vias” assigns non-blocking vias in the layout. The “Mergetrees” links the trees from different metallization layers connected by non-blockingvias. The tree merging process is described in detail in the next section.The steps for reliability analysis in SysRel with the presence of non-blocking viasin a layout are as follows.112Figure 7-3: Menu options for reliability analysis in SysRel with non-blocking vias ina circuit layout.1. Open a circuit layout in SysRel using “File→ Open Magic layout file” menu op-tion. The Magic layout needs to be fully flattened. Non-blocking via assignmentand analysis are not possible with a cell-based hierarchical Magic layout.2. Read the sysrel.emparam file into SysRel using the menu option “File→ ReadEM parameters file”. The technology selection tab in SysRel needs to be set toCu metallization.3. Extract interconnect trees from the layout using the menu option “Electromigration→Extract Failure Units”.4. List and investigate different types of vias used in the circuit layout using themenu option “Non-blocking Via Analysis→ List via types”.5. Assign non-blocking vias in the circuit layout using the menu option “Non-blocking Via Analysis→ Assign non-blocking vias”. The Output Window willlist the number of vias assigned to be non-blocking.6. Merge the interconnect trees connected by non-blocking vias using the menuoption “Non-blocking Via Analysis→ Merge trees”. The Output Window willlist the number of trees in the layout after the tree linking process.7. Continue conventional reliability analysis flow (section 5.5) with the (jmaxL)product filter, (jlocalL) product filter, lifetime calculation of mortal trees, andthen full-chip reliability budget.1137.4 Interconnect Tree MergingThe interconnect trees connected by a non-blocking via are merged to create a singleinterconnect tree spanning multiple layers of metallization. Interconnect tree mergingis a fairly complicated process as all via-to-via paths need to be updated and newvia-to-via paths need to be extracted in a merged tree. Figure 7-4 illustrates the treemerging algorithm with two simple straight line trees A and B.V1 V2V3V3 V4Tree ATree BV1 V2V4Tree C(a)(b)Figure 7-4: Schematic illustration of interconnect tree merging with a non-blockingvia. (a) Tree A and B are linked by non-blocking via V3. (b) Tree C is created afterthe two trees are merged and V3 is removed. The longest path in tree C, used as theeffective length, Lmax, in the immortality condition filter, is now from V2 to V4.The effective length used in the (jL) product filters, in tree A and B are fromV1-to-V2 and V3-V4, respectively. Via-to-via paths in tree A are V1-to-V3, and V3-to-V2. Via-to-via path in tree B is V3-V4. Assuming that V3 is a non-blocking via,V3 is removed from both trees. New paths from V1-to-V4, V2-to-V4, and V1-V2 arecreated. Tree A and B are combined to create a single tree C with the new pathsand tile representations from two layers of metallization (figure 7-4(b)). The effectivelength of tree C is from V2-V4 which is longer than those of tree A or B. The effectivelength in a merged tree either increases or remains unchanged.Interconnect trees are merged recursively until all assigned non-blocking vias are114exhausted in a layout. During this process if a non-blocking via is found in a singlevia tree1, the via is converted to be fully blocking. For example, both vias in aserpentine ring structure in metal2 and metal1 in figure 7-5(a) can be assigned asnon-blocking. However, when the trees are merged, at least one via is required toapply the via-based default model in the merged tree (figure 7-5(b)).(a)(b)Figure 7-5: Dynamic conversion of a non-blocking via to fully blocking via in a mergedtree. (a) A serpentine ring in metal1 and metal2 with two vias assigned to be non-blocking. The longest paths are drawn in the trees. (b) One of the vias is convertedto fully blocking in the merged tree. The non-blocking via is marked in ‘X’.The proper functionality of interconnect tree merging has been carefully traced inSysRel using simple circuit layouts. Figure 7-6 illustrates interconnect tree mergingand its effect in a 3-input nand gate layout with interconnect routing connected to itsoutput. The three inputs are in poly-silicon lines. When all vias are fully blocking,there are eight trees extracted from the layout; one from Vdd, one from Gnd, andthe rests from interconnect routing at the output (figure 7-6(a)). After assigning all1A single via tree is defined as continuous metal segments in one metallization layer with justone via.115possible vias to be non-blocking and merging the trees accordingly, there are threetrees in the layout; one from Vdd, one from Gnd, and one from output routing. Thethree trees and their longest paths are shown in figure 7-6(b).(a) (b)Figure 7-6: Illustration of interconnect tree merging in a 3-input nand gate layout. (a)There are eight trees in the layout. (b) With all possible vias assigned as non-blocking,the number of tree goes down to three. The longest paths are marked.7.5 Line-length Effect on ReliabilityAs illustrated in the previous examples, merging interconnect trees linked with anon-blocking via either increases the effective length in the merged tree or keeps theeffective length unchanged. The increase in effective line length can influence theoutcome of immortality condition filters based on (jL) products. Multiple trees thatwould be immortal with blocking vias can be linked to form mortal trees. However,two or more mortal trees can be linked to form a single mortal tree with a longereffective length. Therefore, the presence of non-blocking vias and interconnect treemerging can lead to either an increase or decrease in the number of mortal trees.In the hierarchical reliability analysis flow, a default model is applied to computethe lifetime of mortal trees. As described in section 2.5, the lifetime of each via ina tree is derived using the equations for time to void nucleation, extrusion, and voidgrowth. The equations in the default model do not take into account the segment-lengths connected to a via; rather a semi-infinite length is assumed that leads toconservative lifetime estimates. Therefore, when the default model is applied to116compute the lifetime of a merged tree, the lifetime is unchanged despite an increasein the effective line length.The effect of interconnect length on lifetime is obvious in experimental work withAl metallization technology. The lifetime of a straight via-to-via Al line as a functionof its length has a trend as shown in figure 7-7(a). At a fixed stress condition, itslifetime (time-to-failure) increases as the length decreases. This is due to the fact thatthe compressive stress developed at the anode end of the line can interact with, andthus slow down the rate of tensile stress increase at the cathode end over a shorterdistance. Figure 7-7(b) shows the time-to-failure of a Cu M1 line as observed inexperimental work reported in [10]. Cu interconnects have a minimum lifetime forintermediate lengths, as the effects of backstress and non-fully blocking boundariesin vias are assumed to increase the lifetime in short and long lines respectively.TTFLcritLength 0 100 200 300 400 500 600 700 800050100150200250300350Time to Failure (hrs)Length ( um) t50 95% confidence interval (a) (b) Figure 7-7: Time-to-failure dependence on interconnect length. (a) Al interconnectshave a minimum TTF for long lines due to absence of the backstress effect; (b) M1Cu interconnects have a minimum TTF for intermediate lengths, as the effects ofbackstress and non-fully blocking boundaries in vias increase the TTF in short andlong lines, respectively. Source: [10].To incorporate one possible impact of increased interconnect length during non-blocking via analysis in SysRel, we have assumed that the time-to-failure in Cuinterconnect is inversely proportional to line length i.e. TTF ∝ (1/L). If a via at theend of an Lref long segment produces a lifetime of TTFref using the default model,117the same via when connected to an Lnew long segment (due to tree merging) wouldhave a lifetime TTFnew computed asTTFnew =(LrefLnew)× TTFref (7.1)Thus a longer interconnect after tree merging would decrease the lifetime accordingto the increase in line length.7.6 32-bit Comparator Layout SimulationThe 32-bit comparator circuit layout discussed in section 5.6 is simulated here to in-vestigate circuit-level reliability impact with non-blocking vias in the layout. Full-chipreliability figures, both including and excluding line length dependence on lifetime ofthe mortal trees, are computed with the percentage of non-blocking via ranging from0% to 100%. The seed for random number generator during non-blocking via assign-ment is set to 223123223. The target lifetime of the chip of 10 years and an uniformtemperature of 105oC are used for these simulations. Table 7.2 lists the simulationresults.When all vias are fully-blocking, the 32-bit comparator circuit layout has eightmortal trees; all from the power delivery, Vdd and Gnd, rings. As the percentage ofnon-blocking vias is gradually increased to 90%, the number of mortal trees decreases.This is because non-blocking vias in the power delivery rings merge multiple treesfrom metal1 and metal2 planes, and eventually results in one mortal tree for Vddand another for Gnd ring. If we ignore the line-length effect on interconnect lifetime,full-chip reliability, in terms of probability of no failure and failure rate, improvesbecause of fewer mortal units as illustrated in table 7.2. However, if the line-lengtheffect is taken into account, the time-to-failure of mortal units decreases according tothe relation in equation 7.1, and the full-chip reliability degrades.When non-blocking via percentages in the layout are set to 90% and 100%, inaddition to the two mortal trees from the power delivery rings, few immortal trees for118Table 7.2: Reliability simulation with various degrees of non-blocking vias in the 32-bitcomparator circuit layout.NB Total # of No line-length dependence With Line-length dependencevia # of mortal TTF (#) Prob. of max TTF (#) Prob. of maxtrees trees years no fail. FIT years no fail. FIT0% 1143 8 23.2 (4) 0.5242 15418 23.2 (4) 0.5242 15418168.7 (4) 168.7 (4)10% 1059 8 23.2 (4) 0.5242 15418 23.2 (4) 0.5242 15418168.7 (4) 168.7 (4)30% 891 7 23.2 (4) 0.5244 15405 12.21 (1) 0.3680 20694168.7 (3) 23.2 (3)168.7 (3)50% 721 3 23.2 (2) 0.7242 7696.1 8.4 (2) 0.1720 26785168.7 (1) 168.7 (1)70% 555 3 23.2 (2) 0.7242 7696.1 8.4 (2) 0.1720 26785168.7 (1) 168.7 (1)90% 393 3 23.2 (2) 0.7244 7683.3 6.42 (2) 0.0854 35037517.8 (1) 517.8 (1)100% 311 4 23.2 (2) 0.7244 7683.4 6.42 (2) 0.0854 35037517.8 (2) 517.8 (2)signal routing get merged and become mortal due to an increase in effective length(figure 7-8). The new mortal trees, however, have fairly high lifetimes due to smallcurrent density in the signal lines, and thus do not degrade the full-chip reliabilitysignificantly.7.7 Discussion of ResultsThe reliability simulation results with the 32-bit comparator layout demonstrate thatthe presence of non-blocking vias overall decreases the number of mortal units. How-ever, merging interconnect trees linked by non-blocking vias increases the effectiveline length of the merged trees. If the default model for estimating the lifetime ofa mortal tree assumes semi-infinite segment lengths, there is a predicted reliabilityimprovement with non-blocking boundaries. However, if the impact of line length istaken into account according to equation 7.1, the full-chip reliability would degrade.The impact of non-blocking vias depends on how reliability depends on length, and1192134Figure 7-8: Mortal trees in the 32-bit comparator circuit layout when all vias areassigned non-blocking. Tree no. 1 and 2 comprise power delivery rings. Tree no. 3and 4 comprise signal routing nets.how non-blocking vias affect the line length dependence of reliability. Figure 7-9 showstwo proposed test structures for investigating line-length dependence of reliability inCu interconnects.7.8 SummarySome electromigration experimental studies postulate that Ta-based liners at thebottom of Cu filled vias in dual-damascene Cu technology do not always block elec-tromigration. Moreover, as the liner thicknesses are decreased in future technologygenerations, fully-blocking liners at vias become less certain due to liner ruptures.We have incorporated into SysRel the capability of reliability simulation with thepresence of non-blocking vias in a circuit layout. Users can stochastically or deter-ministically assign non-blocking vias in the design. Multiple trees, when linked bya non-blocking via, are merged to create a single tree, which is then treated as thefundamental reliability unit. The presence of non-blocking vias leads to either an in-120without blocking boundaries(a) (b)Figure 7-9: Test structures to investigate the line length dependence of reliability inCu interconnects. (a) A long serpentine line in one layer of metallization, and (b) aserpentine line in two layers of metallization linked by multiple non-blocking vias. Thetwo end vias are fully blocking. This structure is to investigate line length dependencein the presence of non-blocking vias.crease or decrease in the number of mortal trees. Trees that would be immortal withblocking vias can be linked to form mortal trees. However, two or more mortal treescan be linked to form a single mortal tree with a longer effective length. The lattereffect results in an overall reduction in the number of mortal trees, as illustrated inSysRel simulation using a 32-bit comparator circuit layout.If the default model for estimating the lifetime of a mortal tree assumes semi-infinite segment lengths, there is a predicted reliability improvement with non-blockingboundaries. However, if the impact of line length is taken into account (e.g., thelifetime to be inversely proportional to line length), the full-chip reliability would de-grade. These results from SysRel demonstrate the critical need for understanding andaccurately modeling the line length dependence on reliability. We have proposed thedevelopment and use of long multiple metal level test structures with non-blockingvias for inter-metal connections and blocking vias at the ends. The results fromsuch test structures would demonstrate line length dependence in the presence ofnon-blocking vias and allow accurate circuit-level reliability assessments with Cumetallization.121122Chapter 8Thermal-Aware ReliabilityAnalysis in SysRelTraditionally, thermal analysis in ICs has been confined to chip-level packaging wherecareful consideration is required for heat sink design [69, 70]. However, as the tech-nology scaling continues, the factors contributing to temperature rise, such as totalpower consumption, power density, and interconnect current density, are consistentlybecoming more and more significant [71]. Consequently, thermal effects have becomeinseparable aspects of IC design and analysis [34, 72]. Interconnect lifetime due toelectromigration is exponentially dependent on inverse temperature. Joule heatingin an interconnect due to its current density can increase the temperature, and thusreduce interconnect reliability. Using a worst case temperature for reliability analysis,and then setting a reliability goal may lead to excessive conservatism in IC design.Therefore, accurate thermal analysis is a prerequisite to circuit-level reliability anal-ysis and reliability-aware IC design. This chapter describes fundamentals of thermalanalysis in the perspective of ICs. Finite element simulations using ANSYS havebeen conducted to investigate thermal effects in transistors. Based on our findings, acell-based technique for estimating layout-level temperature profile is described andimplemented in SysRel. Using the layout-level temperature profile as a boundarycondition, SysRel then incorporates joule heating in interconnects while calculatingthe lifetimes of mortal trees. The 32-bit comparator circuit has been reanalyzed with123thermal capabilities and the results are discussed here.8.1 Fundamental Concepts for Thermal AnalysisThere are three modes of heat transfer: conduction, convection, and radiation [73].Conduction is the mode of heat transfer where energy is exchanged within a solidbody or between two solid bodies in contact due to temperature gradient.Convection is the mode of heat transfer where energy is exchanged between a solidbody and a surrounding fluid.Radiation is the mode of heat transfer from a body or between two bodies byelectromagnetic waves.Thermal analysis in ICs typically involves conduction and convection. Whileconduction is the mode of heat transfer within a die and package, convection is theprimary mode for package-level cooling. Fourier’s law of heat conduction states heatflux, ~q, as following~q = −ki∂T∂i(8.1)where ki is the thermal conductivity and (∂T/∂i) the thermal gradient in directioni. The negative sign indicates that heat flows in the opposite direction of the gra-dient. The SI units for heat flux and thermal conductivity are Watt/meter2 andWatt/meter ·o C, respectively. When heat conducts a distance L from a high to lowtemperature in a body, Fourier’s law is written as~q = k△TL= kThigh − TlowL(8.2)Multiplying both sides with cross-sectional area of the conductor, A,~q × A = kAL△T (8.3)Q =1Rth△T (8.4)124where Q is the heat flow in Watts and Rth is the thermal resistance of the materialin oC/Watt. Equation 8.4 forms the basis of electrical and thermal analogy forconduction as illustrated in table 8.1.Convection is typically applied to heat flow from a surface to neighboring fluid.Newton’s law of cooling states the heat flux due to convection as~q = hf (TS − TB) (8.5)where hf is the convective film coefficient or heat transfer coefficient inWatt/meter2 ·o C,TS is the surface temperature, and TB is the bulk fluid temperature. Considering asurface area, A, for heat flux, we can derive an equation for heat flow, Q, as following~qA = Ahf (TS − TB) (8.6)Q =1Rth(TS − TB) (8.7)where Rth is the thermal resistance for convection. Table 8.1 outlines the electricaland thermal analogy for both conduction and convection.Table 8.1: Electrical and thermal analogy for modeling steady-state heat flow.Electrical ThermalCurrent Flow (I) Heat Flow (Q)Voltage Drop △V = (Vhigh − Vlow) Temperature Drop △T = (Thigh − Tlow)Electrical Resistance (R) Thermal Resistance (Rth)△V = IR △T = QRthR = LσAConduction Rth =LkAConvection Rth =1Ahfσ : electrical conductivity k : thermal conductivityL : length of conductor L: length of conductorA : cross-sectional area A : cross-sectional areahf : convective film coefficientIn steady heat transfer problems, thermal resistance is the most significant phys-ical variable. Modeling unsteady or transient heat transfer problems require thermalcapacitance of an object in addition to its thermal resistance. The rate at which thetemperature of an object rises or decreases is determined by its thermal resistance125and capacitance. The thermal capacitance of an object with volume, V , is expressedasCth = ρmcpV (8.8)where ρm is the material’s density and cp is the heat capacity. The units in SI systemfor Cth, ρm, cp, and V are joule/oC, kg/meter3, joule/kg ·o C, and m3, respectively.The thermal capacitance is considered to be analogous to electrical capacitance tocomplete the electrical and thermal analogy stated in table 8.1.According to the first law of thermodynamics, energy in an object needs to beconserved at any instant. For thermal energy, we can write the energy conservationlaw asEin + Egen = Eout +dEstdt(8.9)where Ein is the thermal energy entering the object, Egen is the thermal energygenerated in the object, Eout is the thermal energy exiting the object, anddEstdtis therate of change in the stored thermal energy. Equivalently,qout − qin = qgen − dEstdt(8.10)∇q = qgen − ρmcpdTdt(8.11)∇ · (−k∇T ) = qgen − ρmcpdTdt(8.12)Assuming the thermal conductivity is uniform in the object−k∇2T = qgen − ρmcpdTdt(8.13)where∇T = ∂T∂x+∂T∂y+∂T∂z(8.14)Equation 8.13 is a simple form of the heat diffusion equation often solved numericallyby using finite difference method for thermal analysis in ICs [74]. The heat diffusionequation is the governing equation for heat conduction problems. The following threeboundary conditions can be applied to the object depending on the surrounding126environment:Isothermal (Dirichlet) : T = f(x, y, z, t) (8.15)Adiabatic (Neumann) : ~q = 0 (8.16)Convective (Robin) : k~q = h(T − Ta) (8.17)where Ta is the ambient temperature.In Finite Element Method (FEM), the governing differential equation, derivedusing the conservation law, is first transformed to an equivalent integral equation. Thegeometric model is discretized into simple shapes, such as rectangles and/or trianglesin 2D, and tetrahedrons, pyramids or hexahedrons in 3D, in which the governingequations are solved [75]. Most FEM tools are capable of non-uniform discretizationor meshing and evaluation of mesh discretization error. Thus, simulation results fromFEM tools are often used as benchmarks for other approaches in IC thermal analysis.In this work, a commercial FEM tool, ANSYS, is used for thermal analysis.The ability to analyze both steady-state and transient conduction and convectionproblems using thermal resistors and capacitors has led to Spice-based thermal sim-ulation of ICs [76]. The substrate is discretized into volumes which is replaced withan equivalent thermal RC network. The power dissipations in devices are representedas current sources in the network. The interconnect lines are replaced with thermalRC transmission lines. T. Chiang et al. have shown that Spice-based simulationresults demonstrate good agreement with Finite Element thermal simulations withANSYS [76]. However, Spice-based simulation is computation intensive and oftenimpractical for large circuit layouts.8.2 Thermal Simulation with ANSYSANSYS, like any FEM simulator, requires geometric input defined by points, lines,areas, or cubes. IC layouts have numerous elements which make it very difficult todraw 3D geometries in ANSYS. Therefore, a program/script is developed to port a127Cadence circuit layout to ANSYS after adding z-dimensions as illustrated in figure 8-1. A user can specify substrate height as an input to the script. The z-dimensionsare derived for 0.18um process technology using metal and via aspect ratios reportedin the ITRS [2]. The script is written in perl, and named cds2inp. The instructionsfor using cds2inp and the script are included in Appendix B.M1Si substrateFigure 8-1: Z-axis dimensions with a substrate height of 10um in cds2inp.In addition to a geometric model, ANSYS requires definitions of several materialparameters. Table 8.2 lists the required material parameters used in this work. Theparameter values are used from [77, 78]. A heat sink is attached to the substratein conventional ICs. Therefore, the substrate is assumed to be the sole heat flowpath to the ambient. Adiabatic boundary conditions are applied at the four sidesand top of the chip, whereas the bottom of the substrate has either convective orisothermal boundary condition. This is a reasonable and widely used assumptionas the chip is enclosed in a thermally insulated packaging material with the bottomsurface attached to a heat sink.A CMOS device from 0.18um process technology with width W = 2um, channellength L = 0.2um, and power dissipation P = 6mW has been simulated in ANSYS.128Table 8.2: Material parameters for thermal simulation in ANSYS.Material Defined propertiesILD SiO2 k = 1.4e− 6 W/um− Cρm = 2650e− 18 kg/um3cp = 753.1 J/kg − CCu k = 390e− 6 W/um− Cρm = 8960e− 18 kg/um3cp = 385 J/kg − CBulk Si k = 120e− 6 W/um− C(for substrate) ρm = 2330e− 18 kg/um3cp = 705 J/kg − CSilicide k = 40e− 6 W/um− C(for PC) ρm = 2330e− 18 Kg/um3cp = 753 J/Kg − CTungsten (W ) k = 170e− 6 W/um− Cρm = 19300e− 18 kg/um3cp = 132 J/kg − CFigure 8-2(a) shows the 3D geometry of the layout with diffusion contacts and metalrouting in ANSYS. The substrate dimension is 20um×20um×10um with an isother-mal (0oC) boundary condition at the bottom. Adiabatic boundary conditions areapplied to the rest of the surfaces. The maximum temperature in the transistor chan-nel, referred to as the junction temperature, is recorded to be 17.3oC from ANSYSsimulation. Figure 8-2(b) and (c) illustrate the temperature profile at the horizontaland vertical cross-sections at the transistor plane, respectively. We see that the tem-perature profile at the top surface of the substrate (transistor plane) in figure 8-2(b)is axisymmetric despite asymmetric metal routing. This is because Si substrate hasapproximately 100 times better thermal conductivity than the ILD material on top.Transistor junction temperature due to self heating is usually reported in termsof oC/mW/um (oC per 1mW power dissipation per 1um width of the transistor)for a fixed channel length. The number is referred to as the thermal resistance ofa device. Using the result from ANSYS, we compute the thermal resistance of thesimulated device to be 5.76oC/mW/um for L = 0.2um. Using reported data from [79],the thermal resistance of a bulk CMOS device with L = 0.2um is calculated to be4.28oC/mW/um which is in close agreement with our simulation result.129(a)(c)(b)0oC17.9oC0oCAxisymmetricT profile in substrateFigure 8-2: ANSYS thermal simulation with a bulk CMOS transistor; (a) 3D geometryof the transistor with metal routing in ANSYS, temperature profile (b) at the topsurface of the substrate (transistor plane), and (c) at the vertical cross-section of theIC.1308.3 Transient Thermal Behavior in Integrated Cir-cuitsSteady-state thermal analysis represents the temperature during static or DC powerdissipation in a circuit. Assuming that the “off” current of a transistor is not highenough to cause self heating, the energy that contributes to a temperature rise isdissipated in digital circuits only when a transistor is switching a node. Figure 8-3 illustrates the power dissipation at the NMOS transistor of an inverter when theoutput node is switching at different frequencies.outputoutputenergyNMOSenergyNMOS½ CV2power=P’power=1.7 P’Figure 8-3: Energy dissipation in the NMOS transistor of an inverter at differentoutput frequencies.To simulate the transient thermal behavior of a transistor, a square wave is usedto define volumetric heat generation rate over time in the channel. The area underthe “on” period in the square wave would represent the amount of energy dissipation.During the “on” period of the square wave, the device temperature increases dueto self heating, and conversely, the “off” period permits cooling. Transient thermalbehavior can be modelled using a thermal time constant, τ , defined as the timerequired for the temperature of a device to increase or decrease by 36.78% (1/e).From a simple transient cooling simulation in ANSYS, we found the thermal timeconstant of the particular bulk CMOS device to be 17.55ns or approximately 20nsused for simplicity in later calculations. When the heat generation square wave in131ANSYS has low enough frequency such that there is enough time for cooling betweentwo pulses, the transient behavior in the device temperature is prominent as shownin figure 8-4. Figure 8-4 illustrates the junction temperature of the device when theinput square has a pulse width 20 times the thermal time constant.Figure 8-4: MOSFET transient temperature plot at 2.5MHz square wave heat gener-ation frequency corresponding to “on” pulse width= 10× τ . Here, τ = 20ns.As we increase frequency of the heat generation square wave in ANSYS, the timebetween heat generation pulses decreases while the representative energy dissipation(total area under “on” periods) per unit time, i.e. the average power, remains un-changed. When the pulse width is (1/40) of the thermal time constant, correspondingto 1GHz frequency of the input square wave, the device temperature reaches a steadystate value over time as illustrated in figure 8-5. By changing the duty cycle of theheat generation square wave, we can represent different average power dissipations ofthe device corresponding to the change in operating frequency of a circuit (figure 8-3).Figure 8-5 shows the device temperature plots at the DC power, average power 1/5 ofDC power, and 1/2 of DC power. With 20% duty cycle, the steady-state temperature132is 3.35± 0.68 oC that can be approximated byTavg =PavgPDCTDC =15× 17.3 = 3.49oCSimilarly, with 50% duty cycle,Tavg =PavgPDCTDC =12× 17.3 = 8.65oCwhereas the simulation shows 8± 0.89 oC.Figure 8-5: MOSFET transient temperature plot at 1GHz square wave heat generationfrequency corresponding to “on” pulse width= τ/40. Here, τ = 20ns.The above simulation results indicate that it is possible to accurately model tran-sient temperature in digital circuits using temperature rise due to DC/static power.When the circuit is operating at a high enough frequency such that there is mini-mal cooling between energy dissipation periods in a device, the device temperaturereaches a steady-state value proportional to the average power. For the simulatedNMOS transistor with thermal time constant of 20ns, an inverter would need to op-erate at 2GHz to maintain τ/40 = 0.5ns between two energy dissipation pulses asused in figure 8-5. If the thermal time constant of a device is higher, for example13350−100 ns reported for silicon-on-insulator devices [80, 81], the circuit operating fre-quency, for which we can accurately model average temperature from average power,would be even lower than 2GHz. Thermal effects are often of major concern and needto be modelled for chips during high frequency operations. Therefore, the methoddescribed here for estimating the steady average temperature from average powerdissipation can by applied to most high performance circuits with excellent accuracy.8.4 Cell-based Thermal Profiling TechniqueFEM simulation or any type of numerical approach for thermal analysis is only ap-plicable to analysis with devices and small circuits. Due to computational cost andlimitation on the number of nodes and memory usage in FEM simulation, ANSYS can-not be used for full 3D analysis with any circuit layout analyzed in SysRel. Therefore,a layout-level temperature profiling technique has been developed and implementedin SysRel. The proposed technique first computes temperature at the top of the sub-strate using the average power dissipation in a cell-based layout, and then, estimatesthe interconnect temperature using a conservative joule heating model.Given the total power dissipation of a circuit, the uniform temperature at thebottom of the substrate is first computed using a simple thermal resistance basedmodel for the heat sink. Figure 8-6 illustrates a conventional heat sink attached tothe bottom of the substrate. The heat sink is replaced with an equivalent 1D thermalresistance, Rhs, connected between the ambient temperature, Ta, and substrate tem-perature, Tsub. The thermal resistance of thermal interface material, used to attachthe heat sink to the chip, can also be placed in series. As reported in [82], an Rhs of0.26oC/W is used in this work for a fin heat sink with air volume flow of 0.006m3/s.Tsub is calculated using equation 8.4 where Q is the total power dissipation of thechip.The uniform substrate temperature at the bottom can now be applied as theisothermal boundary condition to compute the temperature at the transistor planeon top of the substrate. Based on our observations in ANSYS thermal simulations,134Heat SinkchipTaRhsQTsubFigure 8-6: Package-level thermal modeling to compute uniform temperature at thebottom surface of a substrate.the temperature profile due to a power source at the top surface of a substrate is ax-isymmetric and linearly dependent on power. Therefore, temperature can be treatedas a linear and spatially independent variable. We define an impulse response as thetemperature rise at the top of the substrate (transistor plane) due to 1mW of powerdissipation in a unit area (um × um). The impulse response has been constructedfrom ANSYS as shown in figure 8-7. Given a power density profile in a circuit layout,in terms ofmW/um2, we can compute the temperature distribution at the top surfaceof the substrate by convolving the impulse response with the power density profile.Convolution is an O(n2) computational process. Therefore, frequency domain calcu-lation using Fast Fourier Transform (an O(n log2n) process) can be done to reducecomputational load in large circuit layouts.A cell-based approach, compatible with existing IC design flows, has been adoptedto compute the power density profile in a layout. During a large circuit design,cell libraries are typically used where the cells are already characterized for power.Moreover, automated design flows with behavioral level description to synthesis, suchas the one used for designing circuits in this work, explicitly report cell-level powerdissipations using switching activity factors at the nets. The non-uniformity in cell-level power dissipations allows us to capture the non-uniform power distribution ina circuit layout. To compute the power density profile in mW/um2, the averagecell power dissipation is evenly distributed within the cell’s boundary. Ideally, powerdissipation or equivalently heat generation needs to be concentrated into the transistorchannels to capture device self-heating accurately. However, for the sole purposeof modeling interconnect temperature, capturing uniform average temperature in a135Figure 8-7: Thermal impulse response at the top surface of a substrate.cell is computationally efficient. Cell-level uniform temperature assignment has beentraditionally used for fast thermal analysis and temperature driven cell placement [83].The cell-based temperature estimation technique is implemented in a Matlab pro-gram TProfile. The source code for TProfile is included in Appendix C. TProfileaccepts the temperature impulse response and power density matrix as its inputs.The program uses a 2048-pt FFT and inverse-FFT for computing the temperatureprofile matrix. The power density matrix of a single inverter cell (2um× 8um) witha power consumption of 12mW is used to compare TProfile’s temperature estimateswith that from ANSYS simulation. Figure 8-8 and 8-9 show the power density ma-trix and corresponding temperature profile, respectively, in the single inverter cell ina 30um× 30um substrate. The average cell temperatures from TProfile and ANSYSsimulation are 36.3oC and 39.7oC, respectively. The difference is less than 10%.13605101520253005101520253000.10.20.30.40.50.60.70.8x dimension, umPower density matrix of an inverter cell for TProfiley dimension, umpower density (mW/um2 )00.10.20.30.40.50.60.7Figure 8-8: Power density profile of an inverter cell in a 30um× 30um substrate.5101520253051015202530283032343638x dimension, umTemperature (oC) profile of inverter cell layouty dimension, umtemperature (oC)2829303132333435363738Figure 8-9: Temperature profile calculated using TProfile of an inverter cell in a30um× 30um substrate.1378.5 Interconnect Joule HeatingInterconnect joule heating causes the temperature rise due to current flow throughthe metal. As technology scaling progresses, interconnect joule heating effects arebecoming significant due to the increase in current density and number of wiringlevels [84]. In [76], temperature distribution has been modelled in a straight lineinterconnect in the first metal level with two end vias connecting it to the substrate(figure 8-10). Assuming that the substrate temperature is To, via temperature is alsoToTo∆TmaxILDmetal1xT(x)SubstrateFigure 8-10: Modeling the temperature profile in a straight line interconnect connectedto a substrate at temperature To.To due to higher thermal conductively of the vias. Ignoring the effect of variation inmetal resistivity, ρ, with temperature, we can write the diffusion equation asd2Tdx2− T − ToL2H= −ρj2rmskM(8.18)andLH =[kMHtILDkILD(1s)] 12(8.19)where LH is the thermal characteristic length, kM and H are the thermal conductivityand height of the metal line, and kILD and tILD are the thermal conductivity andthickness of the ILD material underneath. The heat spreading factor, s, is used tocorrect the deviation from 1D heat flow between the metal line and the underlying138layer. s = 1 ignores any heat spreading effect and accounts for the worst case tem-perature. It has been shown that within the range of thermal characteristic length,LH , heat can flow through the via. Beyond LH , heat flows through the ILD causingthe maximum temperature rise, △Tmax, at the metal line. △Tmax has been derivedin [76] as following.△Tmax = j2ρL2HkM(8.20)=j2ρHtILDkILDs(8.21)=j2ρHtILDkILD(8.22)Using equation 8.22, we have computed △Tmax in global interconnect lines indifferent technology generations as illustrated in table 8.3. The technology generationparameters are as reported in the ITRS 2003 edition [2]. Interconnect height, H, andILD thickness, tILD, are computed using the minimum global wiring pitch and aspectratio of Cu lines and vias. △Tmax values are computed with two cases of ILD thermalconductivity, kILD; one with projected kILD values used in [84] associated with low-kmaterials, and the other where a fixed kILD value for SiO2 is used in all technologygenerations. The computed △Tmax values in the table suggest that interconnect jouleheating is not significant in near term technology generations; however, it can besevere in future technology generations particularly with low-k ILD materials.Multi-level complex shaped interconnects exist in actual circuit layouts. In Sys-Rel, we model the worst case joule heating at a via while applying the default modelto compute its lifetime. Figure 8-11 illustrates the method for computing via tem-perature at different metal levels. The non-uniform substrate temperature is firstcomputed using the cell-based approach described in the previous section. A via con-nected to the substrate is modelled to be at the same temperature. A higher metallevel via is at a temperature above the substrate temperature by multiples of △Tmax.139Table 8.3: Maximum temperature increase due to interconnect joule heating in differ-ent technology generations.Technology Node 90nm 65nm 45nm 32nm 22nmjmax (MA/cm2) 0.5 1 3 4.3 5.8H (um) 0.4305 0.3190 0.2357 0.1680 0.1250tILD (um) 0.3895 0.2900 0.2153 0.1540 0.1150ρ (µΩ− cm) 2.2 2.2 2.2 2.2 2.2kILD (W/cmoC) 1.4e− 2 1.02e− 2 0.54e− 2 0.19e− 2 0.12e− 2(projected)△Tmax (oC) 0.0659 0.1995 1.8607 5.5391 8.8655kILD (W/cmoC) 1.4e− 2 1.4e− 2 1.4e− 2 1.4e− 2 1.4e− 2(SiO2)△Tmax (oC) 0.0659 0.1454 0.7177 0.7517 0.7599To (x,y)Calculating via temperature123m1m2m3Via 1: Tvia = ToVia 2: Tvia = ∆Tmax + ToVia 3: Tvia = 2∆Tmax + ToILDSubstrateFigure 8-11: Modeling the temperature rise due to joule heating in multi-level inter-connects.8.6 Thermo-file Implementation in SysRelSysRel has a menu bar, named Thermo-file, that adds thermal analysis capabilitiesand a selection tab to disable or enable the thermal-aware analysis using the estimatedtemperature profile. Figure 8-12 shows the menu options available in Thermo-file.Before invoking Thermo-file menu operations, a user needs to open a flattened orhierarchical layout and read the sysrel.emparam file using the “File” menu items inSysRel. The “Read Hierarchical Magic file...” menu item invokes a file chooser dialogbox to allow a user to select the corresponding hierarchical Magic layout file. AThermo-file layout window appears with a cell-level view of the layout. The “ReadPower Distribution (.cpower) File...” menu item invokes a file chooser dialog box toselect a cell-level power report file with the extension .cpower. The .cpower file is anascii text file. Cell-level power dissipation can be computed using either Synopsys140Design Analyzer or Nanosim. The .cpower file, for circuit layouts used in this work,is constructed using cell-level power analysis with Synopsys Design Analyzer.Figure 8-12: Thermo-file menu options in SysRel for thermal-aware reliability analy-sis.The “Write Power Density Matrix (currentpden.m) File” menu item creates apower density map for the cell-based layout using the methodology discussed in sec-tion 8.4. The currentpden.m file is written in user’s current directory. This file servesas an input to TProfile while calculating the layout-level temperature profile usingthe temperature impulse method. TProfile writes an output file, tprofile.dat, thatcan be ported to SysRel using the “Read Temperature Profile Matrix (tprofile.dat)file..” menu item. When the temperature profile is read, the Thermo-file windowupdates the cell-based layout with a color plot of its temperature. The selection tab“Use Thermo-file” in SysRel consequently becomes active. A user can either select toincorporate temperature profile and interconnect joule heating into electromigrationlifetime calculations with “Use Thermo-file: YES” or just use a fixed temperature asdefined in sysrel.emparam file with “Use Thermo-file: NO” option. The reliabilityanalysis follow continues using the “Electromigration” menu.8.7 Thermal-Aware Reliability Simulation with 32-bit ComparatorThe 32-bit comparator circuit described in section 5.6 is used for thermal-aware relia-bility analysis in SysRel. The power density matrix is generated from SysRel and fedinto TProfile to compute the layout-level non-uniform temperature profile as shown141in figure 8-13. With an average power dissipation of 26.6mW , the mortal intercon-nect temperature is only 27.078oC. The lifetimes of mortal trees are significantlyhigher due to such a low temperature rise (table 8.4). Full-chip probability of nofailure within a target lifetime of 10 years is 1. The thermal-aware reliability simu-lation results suggest that full-chip reliability can be pessimistic using a worst caseinterconnect temperature leading to unnecessarily conservative designs.Temperature (oC) Profile of the 32−bit Comparatorx dimension, umy dimension, um27.127.227.327.427.527.6Figure 8-13: Layout-level non-uniform temperature profile in the 32-bit comparatorcircuit layout.8.8 SummaryInterconnect lifetime due to electromigration is exponentially dependent on the inversetemperature. Using a worst case temperature for reliability analysis, and then settinga reliability goal may lead to excessive conservatism in IC design. Therefore, accuratethermal analysis is a prerequisite to circuit-level reliability analysis and reliability-aware IC design. We have conducted ANSYS thermal simulations with a bulk CMOSdevice with metal routing and diffusion contacts. The junction temperature dueto self-heating is in close agreement with reports in other literature. We have alsoconducted transient thermal simulations with the device. It is possible to accurately142Table 8.4: Thermal-aware reliability simulation results with Cu metallization in the32-bit comparator circuit layout.Step 1 Layout Extraction (total # of interconnect trees=1143)Step 2 Via-based (jmaxL) filterNumber of immortaltrees identified1023Step 3 Via-based (jlocalL) filterNumber of immortal trees identified 112Step 4 Default Model (with σnucl = 40MPa) on 8 mortal treest50 of 4 mortal tees in metal1 (via-above) 17484 yearst50 of 4 mortal tees in metal2 (via-below) 103467 yearsStep 5 Full chip stochastic analysis (σ = 0.81, lognormal)Target chip lifetime 10 yearsProbability of no failure 1max FIT 8e− 15t50 for full chip ≫ 10 yearsmodel the transient temperature in digital circuits using the temperature rise due toDC/static power. When the circuit is operating at a high enough frequency such thatthere is minimal cooling between energy dissipation periods in a device, the devicetemperature reaches a steady-state value proportional to the average power.Based on our observations from ANSYS thermal simulations, temperature profiledue to a power source at the top surface of a substrate is axisymmetric and linearlydependent on power. Treating temperature as a linear and spatially independentvariable, we define an impulse response as the temperature rise at the top surfaceof a substrate (transistor plane) due to 1mW of power dissipation in a unit area(um × um). Thus it is possible to compute the temperature distribution at the topsurface of the substrate by convolving the impulse response with the power densityprofile of a layout. A Matlab program TProfile has been developed to compute tem-perature profile using the proposed method in frequency domain. TProfile estimatesthe average temperature of a cell within 10% of that from ANSYS simulation. Us-ing the layout-level temperature profile as a boundary condition, SysRel computesthe interconnect temperature using a conservative joule heating model. The 32-bitcomparator circuit has been reanalyzed with thermal capabilities. While reliabilitysimulation with the worst case interconnect temperature of 105oC predicts full-chip143probability of no failure to be 0.524 for Cu metallization technology, thermal-awarereliability simulation indicates no failure within the chip’s target lifetime.144Chapter 9Reliability Analysis withArithmetic and Logic UnitSysRel reliability simulations discussed in earlier chapters are of rather small adderand comparator circuits. To demonstrate SysRel’s capability and to investigate relia-bility behavior in large circuit layouts, a 64-bit Arithmetic and Logic Unit (ALU) hasbeen designed and analyzed for full-chip reliability. The ALU circuit has been usedto investigate the relative reliability with Al and Cu metallization technologies andto predict future reliability direction with low-k Cu interconnect technology. Thischapter describes the design and analysis work with the 64-bit ALU.9.1 Arithmetic and Logic Unit Design and Syn-thesisAn ALU is the computational core of a processor. A typical ALU performs basicarithmetic functions, such as addition, multiplication, and comparison, as well as ba-sic logic operations, such as AND, OR, and EXOR. The data in an ALU is arrangedas a collection of bits. For instance, a 32-bit ALU operates on 32 bits wide inputs, andproduces a 32 bits wide output. 32-bit datapath is widely used in modern day pro-cessors, although 64-bit datapath is available for very high performance applications.145A 64-bit ALU has been designed and synthesized using a behavioral-level descriptionto synthesis flow. The input instruction is 132-bit wide where the four most signif-icant bits are the opcode1 followed by two 64-bit operands. The input operands, Aand B, and output, C, are signed integer numbers. The behavioral-level descrip-tion of the ALU is written in VHDL modelled after Tiny64, a simple configurablemicroprocessor [85]. Table 9.1 lists the opcodes and their corresponding operations.Table 9.1: Operations in the 64-bit Arithmetic and Logic Unit.Opcode Instruction Description0000 mov Move B to C.0001 and C is A and B.0010 or C is A or B.0011 xor C is A xor B.0100 add C is A+B.0101 sub C is A−B.0110 ror Rotate right A by 1 bit and store in C.0111 lsr Right shift A by 1 bit, pad with 0, and store in C.1000 lsra Right shift A by 1 bit, keep sign unchanged, and store in C.1001 swap Swap most and least significant 32 bits in A and store in C.1010 swapb Swap most and least significant 32 bits in B and store in C.1011 inc C is A+ 1.1100 dec C is A− 1.1101 rorb Rotate right A by 8 bits and store in C.1111 mul C is A(31− 0)×B(31− 0).Using the VHDL description of the ALU, a Verilog gate-level netlist is synthesizedin Synopsys Design Analyzer with the TSMC 0.18um cell library. The Verilog netlistis then placed and routed to create the layout in Silicon Ensemble. Silicon Ensembleoutputs layout in gds2 format which is converted to a Magic format using Magiclayout editor. The 64-bit ALU layout’s dimension is 1035um× 1036um (figure 9-1).Up to five metal levels are used for interconnect routing. The layout has 4193 cells(including filler cells). Table 9.2 shows the number of cells of various types in thelayout.1An opcode is a sequence of bits to indicate designated operations in ALU.146Figure 9-1: The 64-bit Arithmetic and Logic Unit layout in Magic.Table 9.2: The number of cells of various types in the 64-bit ALU circuit.Cell Name Number Cell type NumberXOR2X1 147 XNOR2X1 4OAI21X1 32 NAND3X1 2AOI22X1 136 AND2X1 67INVX1 447 OR2X1 3AOI21X1 14 BUFX2 75NAND2X1 110 FAX1 994NOR2X1 1133 MUX2X1 832INVX2 196 AND2X2 11479.2 Reliability Simulation with Different Metal-lization TechnologiesThe 64-bit ALU circuit is analyzed in SysRel using the cell-based hierarchical layoutfrom Magic. Total power dissipation of 2.129W is estimated using Design Analyzerduring synthesis. The maximum current density in the power delivery lines is ap-proximately 0.46MA/cm2. The worst case interconnect temperature of 105oC andfull-chip target lifetime of 20 years are used for following simulations with the 64-bitALU circuit. The number of tiles representing different mask layers in the layout is807124. Therefore, layout drawing is switched off to minimize simulation time. SysRelreports 89176 interconnect trees in the layout initially outlined in red (figure 9-2(a)).In Cu/SiO2 based interconnect technology, 81619 trees are first identified to be ‘im-mortal’ using the (jmaxL) filter (figure 9-2(b)). Another 6415 trees are filtered outusing the (jlocalL) filter. As illustrated in figure 9-2(c), only 1142 trees are reportedto be mortal in Cu/SiO2 based interconnect technology.(a) (b) (c)Figure 9-2: Immortality in interconnect trees in the 64-bit ALU circuit with Cu met-allization. (a) 89176 trees are extracted from the layout. (b) 81619 trees are identifiedas immortal and outlined in green after (jmaxL) filter. (c) 6415 additional trees areidentified as immortal after (jlocalL) filter. 1142 mortal trees are outlined in red.The 64-bit ALU circuit has been analyzed for full-chip reliability with variousinterconnect technologies. The material parameters used here for diffusivity andlifetime calculations in Al bamboo, Al polygranular, and Cu/SiO2 interconnects are148as reported in tables 4.3, 4.4, 4.5, and 4.6 in Chapter 4. Table 9.3 lists the intermediateresults from immortal tree filtration as well as full-chip reliability in various metrics.Due to higher (jL) product thresholds in Al metallization, only 179 trees are identifiedas mortal. Consistent with our previous analysis, full-chip reliability is the best withAl bamboo type interconnects and worst with Al polygranular type interconnects.On the other hand, lower (jL) product thresholds in Cu/SiO2 based interconnectsidentify 1142 trees to be immortal and predict full-chip reliability to be worse thanthat with Al bamboo type interconnects (row 3 in table 9.3).Table 9.3: Full-chip reliability analysis with the 64-bit ALU in different metallizationtechnologies. Here (jL)M1 and (jL)M2 correspond to (jL)via−above and (jL)via−below,respectively.# of Critical # of # of # of Full-chip reliabilitytrees parameters imm. imm. mortal Prob. of Max t50= 89176 trees trees trees no fail. FIT (years)(jmaxL) (jlocalL)1 Al bam (jL)M1 =(jL)M2 =4000A/cm84724 4273 179 0.994 153 84.12 Al poly σnuc = 500MPa,B = 50GPa84724 4273 179 8.68E − 16 272k 1.073 Cu/SiO2 (jL)M1 =1500A/cm,(jL)M2 =3700A/cm,σnuc = 40MPa,B = 28GPa81619 6415 1142 0.048 25623 8.514 Cu (jL)1 (jL)M1 =(jL)M2 =1500A/cm,σnuc = 40MPa,B = 28GPa78381 9653 1142 0.048 25623 8.515 Cu (jL)2 (jL)M1 =(jL)M2 =700A/cm,σnuc = 40MPa,B = 28GPa67941 18496 2739 0.044 27809 8.506 Cu/low-k (jL)M1 =(jL)M2 =375A/cm,σnuc =12.5MPa,B = 10GPa55134 28710 5332 3.42E − 25 839k 2.33To decrease interconnect delay, a wide range of materials with a low dielectricconstant, κ, generally referred to as low-k dielectrics, are being investigated as re-placements for SiO2. Lower (jL) product thresholds are observed for such ILD ma-terials [86]. Therefore, we have conducted (jL) product sensitivity analysis on thefull-chip reliability of the 64-bit ALU using lower (jL) product thresholds as indicated149in rows 4 and 5 in table 9.3. The number of mortal trees increases with lower (jL)product thresholds which in turn degrades the full-chip reliability.Hau-Riege et al. reported electromigration experimental work on straight linevia-to-via Cu interconnects with a particular low-k dielectric material [87]. They ex-perimentally reported the upper limit of the (jL) product threshold to be 375A/cmand the corresponding critical stress for void nucleation σcrit nuc ≤ 12.5MPa wheninitial stress in the line is zero. In addition, the decrease in dielectric constant cor-responds to a decrease in the elastic moduli of the dielectric material which in turnreduces the effective bulk modulus, B, of the metal-dielectric system. B = 10GPais reported for the Cu/low-k interconnects in [87]. Using the Cu/low-k interconnectsystem in the 64-bit ALU layout, we have analyzed the impact on full-chip reliabilityas illustrated in row 6 in table 9.3. The full-chip reliability is the worst among all oursimulation results. Following are the two contributing factors.• The (jL) product threshold of 375MPa leads to 5332 mortal trees in the 64-bit ALU layout with the Cu/low-k interconnects. The number of mortal treesis approximately 30 times and 5 times more than that with Al and Cu/SiO2interconnects, respectively.• According to equation 2.5, time to void nucleation, tnucl ∝ (sigma2crit nuc/B).A comparatively lower (sigma2crit nuc/B) factor, as computed using the experi-mentally reported data, leads to shorter time to void nucleation in mortal treesin Cu/low-k interconnects. Table 9.4 lists the tnucl and tgrowth values using equa-tions 2.5 and 2.7 of the default model for different interconnect technologies.In void nucleation limited failures, for example, a small void blocking electronflow in Cu via-above type interconnect trees, the lifetime of a mortal tree inCu/low-k is affected most.During SysRel simulations, it is possible to vary any material parameters andinvestigate the impact on full-chip reliability. The reverse is also possible and partic-ularly useful in predicting material and process parameters required to achieve desiredfull-chip reliability. We have conducted similar studies with the 64-bit ALU circuit150Table 9.4: Times to void nucleation and void growth in various interconnect technolo-gies. Here j = 0.5MA/cm2 and T = 105oC.Interconnect technology tnucl tgrowth(years) (years)Al bamboo 164.44 58.99Al polygranular (w = 4um) 2.15 0.77Cu/SiO2 16.19 121.39Cu/low-k 4.42 121.39to investigate the required Cu atomic diffusivity, a parameter that can be controlledduring process development. The full-chip reliability goal is set to the best case prob-ability of 0.994 of no failure within the target lifetime achieved with Al bamboo typeinterconnects. The atomic diffusivity of Cu is varied during simulations using theprescaler, Do, in equation 4.4. The lower the atomic diffusivity, the better the life-time. Initially the diffusivity ratio DAl bamboo/DCu is 0.35. As illustrated in table 9.5,Cu diffusivity needs to be reduced by approximately 12 times to achieve the equiva-lent reliability with Cu/SiO2 based interconnects. With Cu/low-k interconnects, therequired improvement in atomic diffusivity is even higher. Approximately 44 timesdecrease in Cu atomic diffusivity is required with Cu/low-k interconnects.Table 9.5: Cu atomic diffusivity requirements for equivalent circuit-level reliability inthe 64-bit ALU with Al and Cu metallizations.# of Critical # of Prob. Desired Required Requiredtrees parameters mortal of no prob. of diff. ratio decrease in= 89176 trees failure no fail. DAl bam/DCu DCuAl poly (jL)M1 =(jL)M2 =4000A/cm179 0.994 0.994 0.3495Cu/SiO2 (jL)M1 =1500A/cm,(jL)M2 =3700A/cm,σnuc = 40MPa,B = 28GPa1142 0.048 0.995 4.3214 12.36×Cu/low-k (jL)M1 =(jL)M2 =375A/cm,σnuc =12.5MPa,B = 10GPa5332 3.42E − 25 0.995 15.41 44.10×Electromigration tests are usually done with simple interconnect structures. Test-level reliability can be engineered using different fabrication processes and materials,151for example using a different capping layer other than Si3N4 on top of Cu [88], thatimpact critical parameters such as atomic diffusivity and effective modulus. Datain table 9.5 conveys a profound message on the required test-level reliability targetfor Cu metallization technology. Significantly improved test-level reliability in Cuis required to achieve equivalent circuit-level reliability with Al bamboo type inter-connects. Moreover, the required improvement will increase as low-k/low-modulusdielectrics are introduced.9.3 Thermal-Aware Reliability Analysis with the64-bit ALUCell-level power dissipations in the 64-bit ALU are calculated in Design Analyzerduring gate-level netlist synthesis. The default input toggle rate in Design Analyzeris 0.5 in 1ns which corresponds to an operating frequency of 250MHz. Total powerdissipation is reported to be 2.129W when V dd = 5V . Using the cell-level powerdissipations, the layout-level nonuniform power density matrix of the 64-bit ALUis first computed in SysRel. Using the power density matrix in conjunction with atemperature impulse response, the nonuniform temperature profile is calculated inTProfile. Figure 9-3 illustrates the temperature profile in the 64-bit ALU in bulkCMOS technology. There are few hot spots where the temperature rise is as high as4.5oC above the ambient.The average dynamic power consumed in a digital circuit operating at a frequencyf is expressed by the well known relationP = α0→1 × Cload × V dd2 × f (9.1)where Cload is the capacitive load, V dd is the operating voltage, and α0→1 the proba-bility that a power consuming transition occurs at the output [89]. Assuming that theleakage power component does not contribute to significant temperature rise and thedynamic power consumption is dominant, we can estimate power density matrices in152Temperature (oC) Profile of the 64−bit ALUx dimension, 1035umy dimension, 1036um2828.52929.53030.53131.5Figure 9-3: Nonuniform temperature profile of the 64-bit ALU circuit in bulk CMOStechnology at V dd = 5V and operating frequency= 250MHz.the 64-bit ALU at higher operating frequencies using the linear relation depicted inequation 9.1. The power density matrices can then be used to compute layout-leveltemperature profiles at those frequencies. It is important to note that the ALU circuitmay need to be pipelined to operate at higher frequencies and associated circuitrywill add to the total power consumption.Thermal-aware full-chip reliability simulation of the 64-bit ALU circuit has beencarried out in SysRel using Cu/SiO2 based interconnects in the layout. The simula-tions are at various circuit operating frequencies in both bulk CMOS and silicon-on-insulator (SOI) technologies. The temperature impulse response for bulk CMOS tech-nology has been calculated from ANSYS simulation results as discussed in Chapter 8.The thermal resistance of a bulk CMOS device is estimated to be 5.76oC/mW/um.Using the thermal resistance of an SOI device of 50oC/mW/um as reported in [78, 90],we would expect the junction temperature rise in SOI technology to be approximatelynine times of that in bulk CMOS technology. Therefore, the temperature impulse re-sponse is scaled accordingly for estimating temperature profile of the 64-bit ALU in153SOI technology. In addition, circuits in SOI technology can operate at a faster fre-quency than those in comparable bulk CMOS technology due to lower capacitancein SOI devices [91]. As reported in [91], a 64-bit PowerPC in SOI technology has amaximum operating frequency, fMAX , that is approximately 1.24 times the fMAX inbulk CMOS technology. Therefore, we scale the power dissipation in SOI technologyby a factor of 1/1.24 while estimating the power dissipation of the 64-bit ALU circuitoperating at the same frequency as in bulk CMOS technology. Using the estimatedpower dissipation and scaled temperature impulse response for SOI technology, wecompute the temperature profile of the 64-bit ALU circuit for thermal-aware reliabil-ity analysis.Tables 9.6 and 9.7 list the thermal-aware full-chip reliability results in bulk CMOSand SOI technology, respectively, with Cu/SiO2 interconnects in the 64-bit ALU. Tmaxis the maximum temperature at a hot-spot on the substrate. Tavg is the average tem-perature at the top surface of the substrate. The Tmax and Tavg values are stated herefor record. The nonuniform layout-level temperature profile computed for each oper-ating frequency is used during full-chip reliability analysis with SysRel. As indicatedTable 9.6: Thermal-aware full-chip reliability report for the 64-bit ALU with Cu/SiO2metallization in bulk CMOS technology. Here the target lifetime of the chip is 20 years.Operating Bulk CMOS TechnologyFrequency Tmax Tavg Full-chip Max(oC) (oC) prob. of FITno failure250MHz 31.56 27.84 ≈ 1 1.01E − 101GHz 45.26 30.36 ≈ 1 7.56E − 102GHz 63.51 33.72 0.9999 9.6E − 93GHz 81.77 37.07 0.9999 1.41E − 74GHz 100.0 40.43 0.9999 2.95E − 4in table 9.6, the circuit is highly reliable at low operating frequencies in bulk CMOStechnologies. We notice a temperature rise significant enough to degrade reliabilityas indicated by a lower Max FIT only at frequencies such as 3 and 4 GHz. On theother hand, an increased temperature rise in SOI technology significantly affects full-chip reliability at frequencies as low as 1GHz (table 9.7). The maximum hot-spot154temperature reaches higher than the ITRS reported Tmax of 105oC indicating thatactive hot-spot management is required in SOI technology.Table 9.7: Thermal-aware full-chip reliability report for the 64-bit ALU with Cu/SiO2metallization in SOI technology. Here the target lifetime of the circuit is 20 years.Operating SOI TechnologyFrequency Tmax Tavg Full-chip Max(oC) (oC) prob. of FITno failure250MHz 55.94 28.91 ≈ 1 8.88E − 111GHz 142.76 34.63 0.997 68.042GHz 258.51 42.25 2.81E − 27 395kSimulation results in tables 9.6 and 9.7 reiterate the importance of thermal-awarereliability analysis. Electromigration lifetime is exponentially dependent on the in-verse of temperature. At low operating frequencies when power dissipation is nothigh enough, predicted full-chip reliability in the 64-bit ALU is very high. As thetemperature increases with higher performance and power dissipation in the circuit,only then do we observe some degradation in reliability. The reliability degradationis more pronounced in SOI technology where the temperature rise is higher due to anoxide layer underneath the devices.9.4 SummaryA 64-bit Arithmetic and Logic Unit (ALU) has been designed and analyzed for full-chip reliability to demonstrate SysRel’s capability as well as to investigate reliabilitybehavior in large circuit layouts. The layout is 1035um by 1036um in dimensionand consists of 4193 cells. The cell-based layout with various Al and Cu intercon-nect technologies has been analyzed in SysRel. The number of trees is 89176. Theimmortality condition filters indicate that a significant number of trees are indeedimmortal. Moreover, the number of mortal trees is sensitive to the (jL) productthreshold. The higher (jL) product threshold in Al metallization identifies only 179trees to be mortal. On the other hand, the lower (jL) product thresholds in Cu/SiO2155based interconnects lead to 1142 mortal trees. Consistent with our earlier findings,the best full-chip reliability is achieved with Al bamboo type interconnects.The 64-bit ALU circuit has been used to explore future reliability direction withCu/low-k based interconnects. Using experimentally reported parameters for a par-ticular low-k material, we find that the lowest (jL) product threshold in the Cu/low-kbased interconnects leads to the highest number of mortal trees in the layout. In addi-tion, lower lifetimes in the mortal trees generate the worst full-chip reliability metricsamong other types of Al and Cu interconnects. SysRel has been used to investigatethe required improvement in Cu atomic diffusivity such that full-chip reliability canbe matched with the best case with Al bamboo type interconnects. Test-level reli-ability can be engineered by changing parameters, such as Cu atomic diffusivity, inthe interconnects. Our simulation results indicate that significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability withAl bamboo type interconnects. Moreover, the required improvement will increase aslow-k/low-modulus dielectrics are introduced.Thermal-aware full-chip reliability simulation of the 64-bit ALU circuit has beencarried out in SysRel using Cu/SiO2 based interconnects in the layout. The operatingfrequency is varied in the circuit in both bulk CMOS and SOI technologies. Theelectromigration lifetime decreases exponentially with temperature increase. At lowoperating frequencies when the power dissipation is not high enough to generatesignificant temperature rise, predicted full-chip reliability in the 64-bit ALU is veryhigh. As the temperature increases with higher performance, only then do we observenotable degradation in reliability. The reliability degradation is more pronounced inSOI technology where the temperature rise is higher due to an oxide layer underneaththe devices. The simulation results establish that reliability is indeed a concern in highperformance circuits and technology. Moreover, SysRel can demonstrate performance-reliability trade-off in high performance circuits and facilitate reliability-aware circuitdesign.156Chapter 10Conclusions and Future WorkIn the pursuit of higher performance and integration, Integrated Circuit (IC) technol-ogy is heading towards the nanotechnology era. The gate length of a state-of-the-artactive device, such as a metal oxide silicon field-effect transistor (MOSFET), is in therange of 45 to 50 nm allowing millions of such devices to be fabricated in a singlechip. In addition to achieving higher density, smaller devices increase speed due tohigher drive current during the “on” state. While more and more devices are desirablefor integrating more functionality in a single chip, interconnecting the devices usingmetal wires takes up an even greater percentage of space. Interconnect delay relatedto its resistance (R), capacitance (C), and in some cases inductance (L) has becomedominant over gate delay. Cu has been replacing Al as the material of choice forinterconnects due to its lower electrical resistance and expected improved resistanceto electromigration-induced failures. However, with the present fabrication technol-ogy and interconnect architecture scheme, the reliability of Cu interconnects is notas high as it could be.Electromigration experimental work often focuses on via-terminated straight lineinterconnects (figure 10-1(a)). However, in circuit layouts, straight line segments arelinked through junctions to other segments in the same layer or different layers of met-allization. Such junctions are often complex involving multiple linkage to segmentswith different dimensions and current densities. It has been established that an inter-connect tree, a continuously connected piece of metal within one layer of metallization157(figure 10-1(b)), is the appropriate fundamental reliability unit for circuit-level reli-ability assessments for metallization schemes with fully blocking boundaries at thevias. Metal atoms within an interconnect tree can diffuse freely among the segments,and the stress evolutions and atomic fluxes in the segments are coupled. However,most circuit-level reliability assessment tools are still based on breaking up inter-connect trees into individual segments and assessing the reliability of each segmentseparately, using the results from straight via-to-via test lines [33, 34]. This methodis generally inaccurate. Figure 10-1: (a) A simple via-terminated segment used in tests, (b) an example of amore complex interconnect tree on a single level of metallization.Another shortcoming in most existing tools is the treatment of all interconnectlines as being equally prone to electromigration failure. Via-terminated intercon-nect lines can be immune to electromigration-induced failure when operated below acritical product of current density and line length (jL)crit. Rigid vias block electromi-gration and prevent the build-up of high enough mechanical stresses causing failure.Consequently, many interconnects in circuits with either Cu or Al metallization are‘immortal’. Immortality conditions need to be accounted in order for circuit-levelreliability assessments to accurately predict full-chip reliability as well as to manage158workload from numerous interconnect trees in circuit layouts.The present fabrication technology and interconnect architecture scheme for Cuinterconnects lead to distinct electromigration failure characteristics. Cu intercon-nects are fabricated by the damascene method, in which a trench is first etched into ablanket layer of dielectric material before filling it with Cu by electroplating. To pre-vent Cu atoms diffusing into the device layer, thin refractory metal layers consistingof Tantalum (Ta) or Tantalum Nitride (TaN) are placed at the sides and bottom ofthe Cu interconnect lines. Cu-filled vias are used to connect multiple layers of metal-lization. The Cu lines are capped with a dielectric diffusion barrier, which is usuallymade of Silicon Nitride (Si3N4). It has been widely reported that the Cu/Si3N4interface acts both as the dominant diffusion pathway for atoms and as the likely sitefor void nucleation. Gan et al. experimentally demonstrated that, due to this fact,the lifetimes of the M2 test structures were always higher than those of the M1 teststructures with the same length, width, and number of vias at each end [40]. Theunderlying phenomenon applies to all metal layers and has been generalized usingvia-above and via-below definitions.During electromigration in Cu interconnects, a tensile stress develops at the cath-ode end, where the Ta liner underneath a via usually forms a blocking boundaryto diffusing Cu atoms. In via-below structures, voids preferentially nucleate at theCu/Si3N4 interface due to the low critical stress (41 MPa or less) required for thatinterface [43]. An open-circuit failure would occur only when the void grows to spanthe whole thickness of the metal line, resulting in a very large void volume. Onthe other hand, in via-above structures the maximum tensile stress develops at theCu/Si3N4 interface near the cathode via. Therefore, an open-circuit failure wouldoccur if a small void forms below the via, such that the pathway for electron flow isblocked. This asymmetry in the void volume required for failure not only accountsfor the asymmetry in lifetime but also contributes to the different (jL)crit productsin immortality conditions for via-above and via-below type of interconnects.15910.1 Summary and Implications of ResultsIn this work, we have developed a new reliability CAD tool, SysRel, that addressesthe shortcomings of existing tools and incorporates the circuit-level reliability anal-ysis with Cu metallization technology. SysRel applies an interconnect tree basedhierarchical reliability analysis flow with either Al or Cu metallization technology inboth conventional and 3D circuit layouts. Along the tool development work, we haveproposed and implemented various methodologies, such as full-chip reliability anal-ysis, cell-based reliability analysis, layout-level temperature profiling, and reliabilityanalysis with non-blocking via analysis in Cu metallization. Information on SysRelsoftware release is available in Appendix D.10.1.1 SysRel: Interactive Reliability CAD ToolSysRel is an operating system independent stand-alone application written in Java 2.It treats circuit layout files in magic format created with Magic and 3D-Magic. It is aninteractive tool initiating the steps in reliability simulation after receiving user inputsvia menu bars. SysRel has its own desktop which hosts the output window, layoutwindow, and reliability statistics reports after simulation (figure 10-2). A user canseamlessly migrate between Al and Cu metallization technologies in a circuit layoutusing the technology selection tab. Other significant features in SysRel include cell-based and thermal-aware reliability analysis.SysRel utilizes the hierarchical flow for reliability analysis using interconnect treesextracted from circuit layouts as the fundamental reliability unit (FRU). The FRUsare filtered out for immortality in two stages, first using a current density of jmaxfrom the ITRS, and then using jlocal from circuit simulation. Via-type based (jL)product thresholds are applied in the filtering stages for Cu technology. However, nosuch via classification is required for Al technology as a single (jL) product thresholdis sufficient. After the filtering stages, a default model is applied to the mortal FRUsto compute the expected lifetimes due to electromigration failure. Lifetimes are com-bined using a joint stochastic process with a series combination of all FRUs. Given a160Figure 10-2: Screen shot of SysRel desktop pane. At the top right corner are selectiontabs to enable thermal analysis and to select either Cu or Al metallization. Insidethe desktop pane, there are Output Window, Layout Window, Plot Window, and TreeRank Table.161target lifetime for the chip, the full-chip reliability metrics for output are: probabilityof survival, FIT (failure unit) along lifetime, maximum FIT, and time to cumulative% failure. A 32-bit comparator circuit layout in 2D and 3D technology is analyzed inSysRel to demonstrate its basic functionality and significance. SysRel identifies elec-tromigration critical (mortal) trees and allows a designer to focus on those trees whileignoring numerous other immortal trees in the layout. Thus, a “what-if” analysis ispossible on selected mortal trees to observe the impact on full-chip reliability. Thehierarchical reliability flow in SysRel is crucial not only for computational efficiency,but also for accuracy in full-chip reliability analysis. Simulation results with a 64-bitALU circuit demonstrate that 99.8% and 98.7% of the interconnect trees are immortalin Al and Cu metallization, respectively. Therefore, the lack of filtering algorithmsin the flow would produce inaccurate full-chip reliability results.Large circuits are often designed in a hierarchical flow where individual blocks orcells are first designed and characterized. We have developed and implemented in Sys-Rel the concept of cell-level reliability characterization and computationally efficientfull-chip reliability analysis. An IIT standard cell library has been characterized usingSysRel. SysRel reads and retains the hierarchy levels in a hierarchical Magic layout.Reliability simulation results with the hierarchical Magic layouts of a 4-bit adder and32-bit comparator demonstrates the significance of cell-based reliability analysis inSysRel. Statistics from the hierarchical layouts suggest that only a few cells are usedmultiple times and a large percentage of extracted interconnect trees are internal tocells. Therefore, cell-based reliability analysis, where cells are pre-characterized andhidden in a hierarchical layout, improves computational efficiency. The maximumimprovement in times required for layout drawing and interconnect tree extraction of60% and 45%, respectively, have been demonstrated with the 4-bit adder and 32-bitcomparator layouts. The cell-based reliability assessment approach has allowed thesimulation with the fairly large and complex 64-bit Arithmetic and Logic circuit.16210.1.2 Thermal-Aware Reliability Analysis in SysRelInterconnect lifetime due to electromigration is exponentially dependent on the inversetemperature. Therefore, accurate thermal analysis is a prerequisite to circuit-levelreliability analysis and reliability-aware IC design. We have conducted both steadystate and transient thermal simulations with bulk CMOS transistors using ANSYS.It is possible to accurately model the transient temperature in digital circuits usingthe temperature rise due to DC/static power. When the circuit is operating at ahigh enough frequency such that there is minimal cooling between energy dissipationperiods in a device, the device temperature reaches a steady state value proportionalto the average power.Based on our observations from ANSYS thermal simulations, the temperatureprofile due to a power source at the top surface of a substrate is axisymmetric andlinearly dependent on power. Treating temperature as a linear and spatially inde-pendent variable, we define an impulse response as the temperature rise at the topsurface of the substrate (transistor plane) due to 1mW of power dissipation in a unitarea (1um × 1um). Thus it is possible to compute the temperature distribution atthe top surface of the substrate by convolving the impulse response with the powerdensity profile of a layout. A Matlab program TProfile has been developed to com-pute temperature profile using the proposed method in frequency domain using FastFourier Transform. TProfile estimates the average temperature of a cell within 10%of that from ANSYS simulation.Given a cell-based circuit layout and cell-based average power dissipation, SysReloutputs a power density matrix for TProfile. TProfile computes the non-uniformtemperature profile at the top surface of the substrate. Using the layout-level tem-perature profile as a boundary condition, SysRel computes interconnect temperatureusing a conservative joule heating model. Thermal-aware reliability simulation withthe 32-bit comparator layout suggests that using a worst case temperature for relia-bility analysis, and then setting a reliability goal may lead to excessive conservatismin IC design. While reliability simulation with the worst case interconnect temper-163ature of 105oC predicts low full-chip reliability, thermal-aware reliability simulationindicates no failure within the chip’s target lifetime due to low temperature rise.Using the thermal-aware capability in SysRel, we have investigated the thermaleffect from high performance operation and technology, such as silicon-on-insulator(SOI). The operating frequency is varied in the 64-bit ALU circuit in both bulk CMOSand SOI technologies. The electromigration lifetime decreases exponentially due anincrease in temperature. At low operating frequencies when the power dissipationis not high enough, predicted full-chip reliability in the 64-bit ALU is very high.As temperature increases with higher performance, only then do we observe somedegradation in reliability. The reliability degradation is more pronounced in SOItechnology where the temperature rise is higher due to an oxide layer underneath thedevices. The simulation results establish that reliability is indeed a concern in highperformance circuits and technology. Moreover, SysRel can demonstrate performance-reliability trade-off in high performance circuits and facilitate reliability-aware circuitdesign.10.1.3 Reliability Comparison of Copper and AluminumMet-allizationsUnder similar test conditions, electromigration reliability of Al and Cu metallizationinterconnect trees demonstrate significant differences because of the differences in in-terconnect architectural schemes. Using SysRel, we have been able to compare forthe first time circuit-level reliability with the two metallizations. SysRel differenti-ates between Cu and Al technologies during immortality filtering and lifetime esti-mation. Unlike Al technology, a (jL) product filtering algorithm with a classificationof separate via-above and via-below treatments is required in Cu interconnect trees.Different diffusivity mechanisms lead to the differences in electromigration lifetimes.Al lines wider than the grain size (d = 0.5um) have polygranular microstructure withthe highest atomic diffusivity. On the other hand, narrow Al lines with bamboo typemicrostructure have lower diffusivity comparable to that of Cu metallization.Using the best estimates of material parameters, electromigration lifetimes of avia-to-via straight line interconnect are compared for four configurations: Cu via-above, Cu via-below, Al bamboo, and Al polygranular. In typical operating con-dition (j ≤ 0.5MA/cm2 and T ≤ 105oC), an Al bamboo type line has the longesttime-to-failure followed by Cu via-below, Cu via-above, and Al polygranular typelines. Circuit-level reliability simulations with the 32-bit comparator and 64-bit ALUcircuits affirm that the best full-chip reliability is indeed achieved with Al bambootype interconnects. The lower (jL) product thresholds in Cu/SiO2 based intercon-nects lead to an increased number of mortal trees in circuit layouts. Cu/low-k basedinterconnects are reported to have even lower (jL) product thresholds. As predictedusing the default model as well as reported experimentally, mortal trees have shorterlifetimes than Cu/SiO2 based interconnects. Both effects contribute to the worstreliability prediction in the 64-bit ALU circuit with Cu/low-k interconnects.Electromigration tests are done with simple interconnect structures. Test-levelreliability can be engineered using different fabrication processes and materials thatimpact critical parameters, such as atomic diffusivity and effective modulus. Circuit-level reliability comparisons using various circuits and circuit elements in Al and Cumetallizations convey a profound message on the required test-level reliability targetfor Cu. Significantly improved test-level reliability in Cu is required to achieve theequivalent circuit-level reliability with Al bamboo type interconnects. Moreover, therequired improvement will increase as low-k/low-modulus dielectrics are introduced.10.1.4 Non-blocking Via Analysis with Copper MetallizationAn interconnect tree is the fundamental reliability unit for circuit-level reliabilityassessments for metallization schemes with fully-blocking boundaries at the vias. Via-terminated interconnect lines in Al metallization can be immune to electromigration-induced failure when operated below a critical product of the current density and linelength. Tungsten-filled vias block electromigration and prevent the build-up of themechanical stress required to cause failure. In Cu metallization, refractory liners atvias generally block electromigration. However, some experimental studies suggest165that this is not always the case, and as liner thicknesses are decreased, fully-blockingliners at the vias become less certain due to liner ruptures. When Cu-filled vias arenot fully blocking, an interconnect tree is connected to other metallization layers.While liner ruptures can lead to increased lifetimes in test structures, the impactof tree linking on circuit-level reliability is not clear. Therefore, we incorporatedin SysRel a capability for making reliability analysis with non-blocking vias. Userscan stochastically or deterministically assign non-blocking vias in a circuit layout.Multiple trees, when linked by non-blocking vias, are merged to create a single tree,which is then treated as the fundamental reliability unit.The presence of non-blocking vias leads to either an increase or decrease in thenumber of mortal trees. Trees that would be immortal with blocking vias can belinked to form mortal trees. However, two or more mortal trees can be linked to forma single mortal tree with a longer effective length. The latter effect results in an overallreduction in the number of mortal trees, as illustrated with the 32-bit comparatorcircuit layout. If the default model for estimating the lifetime of a mortal tree assumessemi-infinite segment lengths, there is a predicted reliability improvement with non-blocking boundaries. However, if the impact of line length is taken into account(e.g., the lifetime to be inversely proportional to line length), the full-chip reliabilitywould degrade. The impact of non-blocking vias depends on how reliability dependson length, and how non-blocking vias affect the line length dependence of reliability.SysRel simulation results demonstrate the importance of development and use of longtest structures with non-blocking vias for accurate circuit-level reliability assessmentswith Cu metallization.10.2 Potential Applications of SysRelSysRel is a circuit-level reliability assessment tool. Therefore, circuit designers can useSysRel to get interactive feedback on full-chip reliability during design time. SysRelidentifies mortal trees in a circuit layout. Circuit designers can then perform “what-if”analysis with the mortal trees to investigate different methods for potential reliability166improvement. The chief consequences of this research are a design-in reliability tooland associated methodologies. If circuit layouts are not compatible for analysis withSysRel due to layout format, one can still implement the methodologies from SysRelin other circuit-level analysis tools.SysRel is a valuable tool for reliability and process engineers. One can conductsensitivity analysis of material parameters, such as atomic diffusivity, critical stress,and bulk modulus, on full-chip reliability. This would help identify critical processparameters that impact full-chip reliability and allow process engineers to focus onthose for optimum reliability improvement. In addition, SysRel is an ideal tool forpredictive assessment of future technologies currently in development. It is possi-ble to incorporate preliminary models and material parameters for new interconnecttechnologies and investigate the impact on circuit-level reliability.10.3 Future DirectionsThe Reliability CAD tool, SysRel, and associated research work provide the frame-work of future research in various directions.10.3.1 Optimization of SysRelSysRel is written in Java 2. Java programs have been reported to be slow relativeto other languages, such as C++. However, with the advent of just-in-time (JIT)compilers and several source code optimization techniques, the performance of Javaprograms can be significantly improved [92]. As SysRel has been developed as a pilotRCAD tool, only a few critical operations, such as Magic layout out parsing, areoptimized for speed and memory usage. Further optimization is possible and wouldbe essential for analysis with large fully flattened circuit layouts. In fact, non-blockingvia analysis with the 64-bit ALU circuit was not feasible with the current version ofSysRel due to long simulation time. Performance bottlenecks in SysRel need to beidentified using a Java profiler tool, for example JProfiler [93]. Data-structures andalgorithms can be optimized for fast interconnect tree extraction and layout drawing.167Several pointers for optimizing Java codes for speed and memory usage are availableat [94, 95].Another venue for improvement in SysRel is the development of sophisticatedmethodologies for local current density calculation in interconnect trees. While cur-rent density calculation in power delivery lines (unidirectional current flow) are rela-tively straight forward, segment-based current density estimation in signal networksis an active area of research [57]. Signal networks carry a combination of bidirectionaland unidirectional currents in different segments. Detail current flow information in-cluding current directions in different segments of an interconnect tree is not availablefrom any power analysis tool, and more importantly, simple algorithms are often notcomputationally feasible for application in a large circuit layout.10.3.2 Enhanced Electromigration Lifetime ModelSysRel uses a default model for estimating electromigration lifetime at the vias origi-nally developed for Al metallization, and then extended for Cu metallization technol-ogy [18, 41]. When compared to experimental lifetime results, the default model givesa conservative lifetime prediction for an interconnect tree. Moreover, the model as-sumes semi-infinite segment lengths while calculating the lifetime of a via connectingthose segments. As indicated in this work, the line length effect on electromigrationlifetime is a significant factor for accurate assessment of the impact of non-blockingvias in Cu metallization technology. Therefore, the line length dependence needs tobe investigated for incorporation into the default model.The default model for computing the lifetime of a via is appropriate for a singlevia at junctions as shown in figure 10-1(b). While such single via junctions are morecommon in signal lines, power delivery and clock lines are often wider with multiplevias at a junction. As illustrated in figure 10-3, multiple vias are used to reducethe current density through each via and to reduce the electrical resistance of thejunction. Current implementation in SysRel lumps all vias into one and uses thecurrent density computed for a single via. This is a conservative approach that doesnot take into account the effect of parallel paths in the junction. Experimental work168is required to characterize the impact of multiple vias on electromigration lifetime.The default model needs to be upgraded accordingly.Figure 10-3: Multiple vias at a junction in wide metal interconnects.The electromigration failure mechanisms and characteristics may change in futurewith the advent of low-k dielectric materials in Cu metallization technology. It hasbeen reported that the electromigration lifetime of Cu/low-k interconnects is shorterthan Cu/SiO2 and that extrusions are more frequently seen at the anode end of theline during failure analysis [96]. The electromigration lifetime needs to be remodelledto account for new findings in future interconnect technologies. New models can beeasily incorporated into SysRel to assess circuit-level reliability.10.3.3 Thermal Analysis and Management in 3D IC Tech-nologySysRel currently has the capability for thermal-aware reliability analysis with conven-tional or 2D circuits. Thermal modeling and analysis that incorporates new thermalmanagement strategies in 3D ICs is a promising area of research. SysRel provides theframework for layout-level thermal profiling in 3D circuit layouts created using 3D-Magic. A new 3D integration scheme with face-to-face bonds for high density inter-wafer connections and back-to-back bonds with embedded micro-channels (thermal169connects) at the Si interface has been proposed in section 1.4.3. Future research workwith the 3D integration scheme can include fabrication and experiments with bondedwafers to quantify bonding strength in the presence of micro-channels. In addition,new thermal modeling techniques need to be developed that generate layout-leveltemperature profiles in 3D. The layout-level temperature profile in 3D circuits needsto incorporate nonuniform power dissipation in both horizontal and vertical planes.One can also develop methodologies for the optimal placement of micro-channels inthe presence of nonuniform power dissipation. It would be interesting to incorporatethermal analysis capabilities for 3D ICs into SysRel and investigate the reliabilityimpact from the proposed thermal management technique.10.3.4 Impact of Process VariationsDue to process variations in advanced technologies, interconnect parameters, such asILD thickness, metal height, and metal resistivity, are stochastic in nature [97]. Con-sequently, CAD simulation results may vary from Si implementations if the processvariation effects are not taken into account. According to [98], the most commonexamples of deviations related to interconnect technology include reliability effectssuch as signal electromigration, power electromigration and IR drop, crosstalk glitch,and crosstalk delay. If the uncertainly is not taken into account, circuit design maylead to be either less reliable than expected or excessively conservative trading offmaximum attainable performance. SysRel, being a layout-level analysis tool, has theframework to incorporate the effects of process variations. Interconnect pattern den-sity, a contributing factor in interconnect parameter variations, is readily availablefrom circuit layouts in SysRel [98]. Instead of using fixed values for ILD thickness,metal height, and metal resistivity, one can extend SysRel to include associated dis-tributions for stochastic analysis. Using the extended SysRel, it will be interesting toquantify circuit-level reliability impact in the presence of process variations.170Appendix ASysRel Source Code OverviewThis appendix contains an overview of SysRel’s source code in Java. The source codeis available from Prof. Donald E. Troxel or Prof. Carl V. Thompson at MIT [99].The code is written in Java 2. The Java classes are categorized into functional groups.The major functionalities and features of the classes, defined in the java file, class-name.java, are briefly described under each category.A.1 Main Application ClassesThe main application classes are responsible for starting the SysRel application whenit is invoked from the command line or by double clicking the jar file. These classesalso define global variables for use in the rest of the application.SysRel.java SysRel.java is the topmost class of SysRel. The primary function ofSysRel is to invoke the graphical user interface. Menu bars and corresponding actionlisteners are defined in SysRel.java. SysRel uses multiple document interface (MDI)functionality to keep the internal modules, such as layout window, thermo-file window,and output window, centrally contained within the master application’s window.Globals.java This class contains the declaration for global constants, runtime vari-ables, and debugging flags for use in the entire SysRel application.171A.2 Graphical Interface ClassesThe graphical interface classes are developed using the Java Swing package avail-able in Java Development Kit (JDK) version 1.3 [63]. Swing supports everythingfrom creating menus, dialog boxes, and buttons in a Graphical User Interface (GUI)application.MyLayoutFrame.java The MyLayoutFrame class extends or inherits from JIn-ternalFrame class in Swing. This class is responsible for creating the layout windowinside the SysRel desktop. MyLayoutFrame defines and supports basic menu opera-tions for viewing a layout, such as zoom in, zoom out, zoom fit, and pan left, right,top, and bottom. Other menu operations include selecting different levels of hierar-chy if a cell-based hierarchical Magic layout file is opened in the layout window. Thethird menu option lists all metal levels used in the layout and allows a user to electeither all levels or any one level for interconnect tree extraction.LayoutPanel.java The LayoutPanel class inherits from the Swing JPanel class andprovides infrastructure to display a layout in a scrollable window. The class has itsown Graphics2D1 object and a paint method to handle all rectangle drawing tasks.MyThermoFrame.java The MyThermoFrame class extends JInternalFrame. Thepurpose of this class is to create a thermo-file window in SysRel that displays cell-level view of the layout with its temperature profile. Similar to MyLayoutFrame,MyThermoFrame defines and supports basic menu operations for viewing the layout,such as zoom in, zoom out, zoom fit, and pan left, right, top, and bottom.ThermalPanel.java The ThermalPanel is equivalent to LayoutPanel class respon-sible for displaying the cell-based layout and temperature profile in the thermo-filewindow. The class has its own Graphics2D object and a paint method.1The Graphics2D class is the abstract base class of Java for all graphics contexts that allows anapplication to draw onto components.172MyOutputFrame.java The MyOutputFrame class extends JInternalFrame andis responsible for creating the output window in SysRel’s desktop pane. The classsupports a scrollable text area in the output window.A.3 File Parser ClassesThe file parser classes primarily serve two purposes, parsing the Magic technologyand layout files. While creating a layout window, MyLayoutFrame instantiates thefile parser objects.TechDB.java The TechDB class implements a recursive parser for reading Magic’stechnology file. The main constructor for the class is called with a string represen-tation of technology file’s Uniform Resource Locator (URL2). This allows SysRel toincorporate a technology file from anywhere in a networked system. An InputStream3object is created from the URL for reading the ASCII representation of a technologyfile. Then all the sections in a technology file are parsed using the parser meth-ods, and information on different planes, tiles, and contacts are stored in Hashtable4data-structures.ParseMAGFile.java The ParseMAGFile class implements the recursive parser forreading a Magic layout or a .mag file, and works in a similar fashion as TechDB. Givenan URL, it opens a .mag file, and conditionally calls its parser methods, ParseSec-tion(), ParseRect(), or ParseRLabel(), depending on what ParseLine() interprets fromthe current line in the file. All parsed information is “cached” internally to reducethe amount of time required for parsing large layouts. Following classes implementthe cached representation of layout data.2An URL is a pointer to a “resource” on the World Wide Web. A resource can be something assimple as a file or a directory.3A superclass of all classes representing an input stream of bytes in Java.4Hashtable is a Java data-storage class that maps distinct keys to stored values.173CachedSection.java This class implements the object representation of a “sec-tion” in a .mag file. A section in a Magic file is defined to start with a “<< foo>>”, where “foo” is the name of a mask layer (e.g. polysilicon, metal1, etc.) or somecontrol sections (e.g error s, checkpaint, end). A CachedSection object contains allthe coordinates of rectangular tiles that follow the section header tag.CachedStmt.java The CashedStmt class implements the cached representation ofany statement that is in .mag file’s sections. It is an abstract type that must besubclassed to CachedRect, CachedRLabel, or CachedUse.CachedRect.java This class extends the CachedStmt class. Given the parsed co-ordinates from the “rect ll lr ul ur” statement in a “section” of a .mag file, it definesa rectangular tile representing a mask layer.CachedRlabel.java The CachedRlabel class extends CachedStmt, and implementsthe object representation for an “rlabel” statement in a section. The “rlabel” state-ment assigns user defined text labels to mask layers in a layout file.CachedUse.java The CachedUse class also extends CachedStmt, and implementsthe object representation for an “use” statement in a .mag file. The “use” statementallows users to import instances of another .mag file into the layout.CachedCell.java Finally, the CachedCell class implements the cached representa-tion of the entire .mag file. A CachedCell contains multiple instances of Cached-Section, CachedStmt, CachedRect, CachedRlabel, and CachedUse to fully define alayout. In a hierarchical layout, where a .mag file imports other .mag files, theCachedCell object for the parent layout has pointers to other CachedCell objects forthe sub-layouts.174A.4 Corner-stitched Data-structure ClassesThese classes define corner-stitched data-structure for the internal representation ofa layout file. The corner-stitched data-structure is described in section 5.3.Tile.java The Tile class implements the basic representation of a corner-stitched“tile” object in a layout. A “tile” is a rectangle corresponding to either a mask layeror, in case of a “space tile”, absence of it. The Tile class contains “pointers” to eighttiles adjacent to the corner-edges. The neighboring tiles are stored in an array tofacilitate faster search algorithms.TileType.java The TileType class implements different categories of tiles in a par-ticular layout. The different categories are defined according to the input from “types”and “contact” sections in a technology file. For every instance of a Tile class, thereis a TileType object to represent its mask layer, such as metal1, poly, and metal2.Plane.java The Plane class inherits from Tile, and represents a collection of Tileobjects, including “space”, that exists in any particular plane of a layout. Initially, aplane is a large “space tile” representing the absence of mask layers. As a layout isparsed, solid tiles are added to this large space plane at the proper positions.PlaneType.java Similar to the TileType class, this class implements different cat-egories of planes in a particular layout. The planes are defined according to the inputfrom the “planes” section in a technology file.A.5 Layout and Tree Representation ClassesThe layout and tree representation classes implement the internal representation ofa parsed .mag file with the corner-stitched data-structures. These classes also storethe interconnect trees for further analysis.175Layout.java The Layout class defines a layout as a stack of multiple Plane objectswhere an individual Plane object has different types of Tiles to represent the masklayers. The constructor for this class takes CachedCell and TechDB objects as itsinput parameters for creating such a representation.ITree.java This class represents an interconnect tree built from corner-stitchedlayout representation. An interconnect tree is stored as a collection of adjacent tilesthat would form a continuous electrical path in one layer of metallization.ISegment.java The ISegment class implements a Tile that is a part of an ITree.The ISegment class allows differentiation of Tile objects based on whether they forman interconnect tree or not. An ISegment object is specially tagged if it is a contacttile in a tree.ISurface.java This class implements the surface area between adjacent ISegmentsin an ITree. The ISurface class can be used for generating tree input data for MITEMSIM [50].Path.java The Path class inherits a Vector5 class and defines a specific path alongan ITree object. It consists of a sequence of ISurfaces between starting and end-ing ISegments. An ITree object can have multiple paths as more than one endingISegments can exist in an interconnect tree.CellView.java The CellView class supports the cell representation in a hierarchicalcell-based magic layout. In a cell-based layout, each cell has a CellView object withits own Tiles and Planes arrays. Multiple CellView objects are linked to the rootCellview. In case of a flattened layout, only one CellView object is created to representthe root layout.5The Vector class in Java implements a growable array of objects. Like an array, it containscomponents that can be accessed using an integer index.176A.6 Reliability Computation ClassThe reliability computation class is responsible for defining the methods and associ-ated algorithms for reliability analysis. Only this class needs to be extended to addmore features and new models in future.Reliability.java The Reliability class implements the methods that operate onITree objects and apply different filtering algorithms to isolate mortal interconnecttrees. Methods, such as applyJmaxLfilter(), applyRandomBC(), and applyExtrac-tion(), are called when the main application invokes reliability analyses from the“Electromigration” menu. The Reliability class contains values for technology-specificmaterial parameters. Using the values, the method applyDefaultModel() computes thelifetime of mortal trees in Cu or Al metallization technology depending on the currenttechnology selection. The Reliability class also supports non-blocking via analysis.The methods generateNBvias() assigns non-blocking vias in a flat layout with Cumetallization and joinTrees() creates merged trees linked by non-blocking vias.177178Appendix BCadence to ANSYS GeometricModel Conversion: cds2inpThis appendix contains the perl script, cds2inp, that converts a Cadence circuit layoutto ANSYS input file defining a 3D geometric model. Figure B-1 shows an exampleof the conversion using a transistor layout with diffusion contacts and metal routing.The Cadence circuit layout needs to be saved in an ascii text file. The instructionsfor using cds2inp are as follows:1. Draw an outline or ESEXCL layer in the Cadence layout to indicate a boundaryfor the substrate in ANSYS simulation.2. Move the origin to the lower left corner of the outline. Use menu operations:Edit→Other→Move Origin.. (to define a simple coordinate system in ANSYS)3. Select layers, including the outline, for converting to ANSYS geometry. Toselect all layers in the layout, use menu operations: Edit→Select All.4. From the Window menu in Cadence, select “Show Selected Set”. This will opena new window with the text representation of selected layers.5. Save the text in a file, such as file1.out, as text format (default) using the Filemenu in the opened window. Copy the saved file to cds2inp script’s directorylocation.1796. Run “cds2inp file1.out file2.inp [optional arguments]”. Run “cds2inp” to see alist of all optional arguments. File2.inp is the output file name to be created.7. cds2inp reads material properties from /materials/*.mat files. A single .mat filedefines desired material properties for a give material.8. After starting ANSYS, read “file2.inp” using the File menu’s “read from file”option. This would create the geometry and define material properties auto-matically.ANSYS GeometryCadence LayoutFigure B-1: Cadence circuit layout to ANSYS geometry conversion demo with a tran-sistor with diffusion contacts and metal routing.Perl script for cds2inpuse strict;use warnings;print "\n\n";print "Starting the Cadence layout to ANSYS input geometryconverter\n";print "Author: Syed M. Alam\n";print "Last Modified @ MIT:November 7, 2003\n";180print "Usage: cds2inp ascii_layout outputfile [sub1_thickness in um][3d] [ff/bb/fb] [sub2_thickness in um]\n";print "Bulk CMOS Technology\n"; print "----------------------------\n";my $sub1_h; #default substrate_1 height is 10um$sub1_h=10;if ($ARGV[2] && $ARGV[2]>0) {$sub1_h=$ARGV[2];}#Add more layers and z-dimensions here in ummy @layers=qw(ESEXCLDIFF CONT POLY1 METAL1 ILD);#original layers, working for these layers as well#my @layers=qw(OUTLINE RX CA PC M1 ILD);# thickness of layersmy %layer_h= ( ESEXCL => 0,DIFF => 0.12,CONT => 0.68,POLY1 => 0.34,METAL1 => 0.50,ILD => 2.00);my %layer_z1= ( ESEXCL => 0,DIFF => ($sub1_h-$layer_h{DIFF}),CONT => $sub1_h,POLY1 => $sub1_h,METAL1 => ($sub1_h+$layer_h{CONT}),ILD => $sub1_h);my %layer_z2= ( ESEXCL => $sub1_h,DIFF => $sub1_h,CONT => ($sub1_h+$layer_h{CONT}),POLY1 => ($sub1_h+$layer_h{POLY1}),181METAL1 => ($sub1_h+$layer_h{CONT}+$layer_h{METAL1}),ILD => ($sub1_h+$layer_h{ILD}) );if (!$ARGV[0]) {print "Thank you for using cds2inp. See usage forcommand line arguments\n\n"; exit;}my $temp_v = 0; my $inputfile=$ARGV[0]; my $outputfile=$ARGV[1];my $tdic; my $tdic_bond; my $sub2_h;# default substrate 2 height is 10um $sub2_h=10; # dafault bondingscheme is fb $tdic_bond="ff";if ($ARGV[3] && $ARGV[3] eq "3d") {$tdic=1;} else {$tdic=0;} if($ARGV[4]) {$tdic_bond=$ARGV[4];} if ($ARGV[5] && $ARGV[5]>0){$sub2_h=$ARGV[5];}# z-dimensions for face-to-face bondingmy %layer_ff_z1= ( ESEXCL => ($layer_z2{ILD}+$layer_h{ILD}),DIFF => ($layer_z2{ILD}+$layer_h{ILD}),CONT => ($layer_z2{ILD}+$layer_h{ILD}-$layer_h{CONT}),POLY1 => ($layer_z2{ILD}+$layer_h{ILD}-$layer_h{POLY1}),METAL1 => ($layer_z2{ILD}+$layer_h{ILD}-$layer_h{CONT}-$layer_h{METAL1}),ILD => $layer_z2{ILD} );my %layer_ff_z2= ( ESEXCL => ($layer_z2{ILD}+$layer_h{ILD}+$sub2_h),DIFF => ($layer_z2{ILD}+$layer_h{ILD}+$layer_h{DIFF}),CONT => ($layer_z2{ILD}+$layer_h{ILD}),POLY1 => ($layer_z2{ILD}+$layer_h{ILD}),METAL1 => ($layer_z2{ILD}+$layer_h{ILD}-$layer_h{CONT}),182ILD => ($layer_z2{ILD}+$layer_h{ILD}) );# z-dimensions for face-to-back bondingmy %layer_fb_z1= ( ESEXCL => $layer_z2{ILD},DIFF => ($layer_z2{ILD}+$sub2_h-$layer_h{DIFF}),CONT => ($layer_z2{ILD}+$sub2_h),POLY1 => ($layer_z2{ILD}+$sub2_h),METAL1 => ($layer_z2{ILD}+$sub2_h+$layer_h{CONT}),ILD => ($layer_z2{ILD}+$sub2_h) );my %layer_fb_z2= ( ESEXCL => ($layer_z2{ILD}+$sub2_h),DIFF => ($layer_z2{ILD}+$sub2_h),CONT =>($layer_z2{ILD}+$sub2_h+$layer_h{CONT}) ,POLY1 => ($layer_z2{ILD}+$sub2_h+$layer_h{POLY1}),METAL1 =>($layer_z2{ILD}+$sub2_h+$layer_h{CONT}+$layer_h{METAL1}),ILD => ($layer_z2{ILD}+$sub2_h+$layer_h{ILD}) );# z-dimensions for back-to-back bondingmy %layer_bb_z1= ( ESEXCL => -$sub2_h,DIFF => -$sub2_h,CONT => (-$sub2_h-$layer_h{CONT}),POLY1 => (-$sub2_h-$layer_h{POLY1}),METAL1 => (-$sub2_h-$layer_h{CONT}-$layer_h{METAL1}),ILD => (-$sub2_h-$layer_h{ILD}) );my %layer_bb_z2= ( ESEXCL => 0,DIFF => (-$sub2_h+$layer_h{DIFF}),CONT => -$sub2_h,POLY1 => -$sub2_h,METAL1 => (-$sub2_h-$layer_h{CONT}),ILD => -$sub2_h );183print "Openning File: $inputfile\n"; open RFILE, "< $inputfile" ordie "Can’t open input file:\n$!"; print "Openning File to Write:$outputfile\n"; open WFILE, "> $outputfile" or die "Can’t openoutput file:\n$!"; writeheader(); while (my $line=) {$line=~ s/:/ /;$line=~ s/:/ /;my @larray = split(" ",$line);if ($larray[0] && $larray[0] eq "rect") {my $wline = block(@larray);if ($wline) {print "Write: $wline";print WFILE "$wline"; $temp_v=1;}}} writefooter(); close WFILE; close RFILE; if($temp_v==0) {print "WARNING: No geometric data in $outputfile\n";print "WARNING: Removing $outputfile\n";#rm $outputfile;} else{ print "$outputfile written properly for ANSYS\n" }sub block {my @larray=@_;my $solid = $larray[1];if ($solid eq "PC") {$solid="POLY1";}if ($solid eq "M1") {$solid="METAL1";}if ($solid eq "RX") {$solid="DIFF";}184if ($solid eq "OUTLINE") {$solid="ESEXCL";}if ($solid eq "CA") {$solid="CONT";}if (!grep(/$solid/, @layers)){ return;}print "Read: @larray\n";my $x1=$larray[4];$x1=~ s/://;my $x2=$larray[6];$x2=~ s/://;my $y1=$larray[5];my $y2=$larray[7];my $z1=$layer_z1{$solid};my $z2=$layer_z2{$solid};if ($solid eq "ESEXCL") {if ($tdic) {if ($tdic_bond eq "ff"){ return "block,$x1,$x2,$y1,$y2,$z1,$z2\nblock,$x1,$x2,$y1,$y2,$layer_z1{ILD},$layer_z2{ILD}\nblock,$x1,$x2,$y1,$y2,$layer_ff_z1{ESEXCL},$layer_ff_z2{ESEXCL}\nblock,$x1,$x2,$y1,$y2,$layer_ff_z1{ILD},$layer_ff_z2{ILD}\n"; }if ($tdic_bond eq "fb"){ return "block,$x1,$x2,$y1,$y2,$z1,$z2\nblock,$x1,$x2,$y1,$y2,$layer_z1{ILD},$layer_z2{ILD}\nblock,$x1,$x2,$y1,$y2,$layer_fb_z1{ESEXCL},$layer_fb_z2{ESEXCL}\nblock,$x1,$x2,$y1,$y2,$layer_fb_z1{ILD},$layer_fb_z2{ILD}\n"; }if ($tdic_bond eq "bb"){return "block,$x1,$x2,$y1,$y2,$z1,$z2\nblock,$x1,$x2,$y1,$y2,$layer_z1{ILD},$layer_z2{ILD}\nblock,$x1,$x2,$y1,$y2,185$layer_bb_z1{ESEXCL},$layer_bb_z2{ESEXCL}\nblock,$x1,$x2,$y1,$y2,$layer_bb_z1{ILD},$layer_bb_z2{ILD}\n"; }}else{ return "block,$x1,$x2,$y1,$y2,$z1,$z2\nblock,$x1,$x2,$y1,$y2,$layer_z1{ILD},$layer_z2{ILD}\n";}}if ($tdic) { #if tdic then have 2 block statements for each solidif($tdic_bond eq "ff"){return "block,$x1,$x2,$y1,$y2,$z1,$z2\nblock,$x1,$x2,$y1,$y2,$layer_ff_z1{$solid},$layer_ff_z2{$solid}\n"; }if($tdic_bond eq "fb"){ return "block,$x1,$x2,$y1,$y2,$z1,$z2\nblock,$x1,$x2,$y1,$y2,$layer_fb_z1{$solid},$layer_fb_z2{$solid}\n"; }if($tdic_bond eq "bb"){ return "block,$x1,$x2,$y1,$y2,$z1,$z2\nblock,$x1,$x2,$y1,$y2,$layer_bb_z1{$solid},$layer_bb_z2{$solid}\n"; }}#not a tdic, just return one block statementreturn "block,$x1,$x2,$y1,$y2,$z1,$z2\n";}sub writeheader {print WFILE "/TITLE,Thermal Analysis File\n";print WFILE "KEYW,PR_SET,1\n";print WFILE "KEYW,PR_STRUC,0\n";print WFILE "KEYW,PR_THERM,1\n";186print WFILE "KEYW,PR_FLUID,0\n";print WFILE "KEYW,PR_ELMAG,0\n";print WFILE "KEYW,MAGNOD,0\n";print WFILE "KEYW,MAGEDG,0\n";print WFILE "KEYW,MAGHFE,0\n";print WFILE "KEYW,MAGELC,0\n";print WFILE "KEYW,PR_MULTI,0\n";print WFILE "KEYW,PR_CFD,0\n";print WFILE "/GO\n";print WFILE "!*\n";print WFILE "/COM,\n";print WFILE "/COM,Preferences for GUI filtering set to display:\n";print WFILE "/COM, Thermal\n";print WFILE "!*\n";print WFILE "/PREP7\n";print WFILE "!*\n";print WFILE "ET,1,SOLID90\n";print WFILE "!*\n";print WFILE "mat,1\n";print WFILE "mpread,materials/SiO2.mat,,,\n";print WFILE "mat,2\n";print WFILE "mpread,materials/Cu.mat,,,\n";print WFILE "mat,3\n";print WFILE "mpread,materials/bulkSi.mat,,,\n";print WFILE "mat,4\n";print WFILE "mpread,materials/channelSi.mat,,,\n";print WFILE "mat,5\n";print WFILE "mpread,materials/poly.mat,,,\n";print WFILE "mat,6\n";187print WFILE "mpread,materials/W.mat,,,\n";}sub writefooter {print WFILE "/VIEW, 1 ,1,1,1\n";print WFILE "/ANG, 1\n";print WFILE "/REP,FAST\n";print WFILE "/GRAPHICS,POWER\n";print WFILE "!*\n";print WFILE "/TYPE,1,8\n";print WFILE "/CPLANE,1\n";print WFILE "/SHADE,1,1\n";print WFILE "/REPLOT\n";print WFILE "VOVLAP,ALL\n";print WFILE "NUMM,KP\n";print WFILE "!*\n";print WFILE "/PNUM,KP,0\n";print WFILE "/PNUM,LINE,0\n";print WFILE "/PNUM,AREA,0\n";print WFILE "/PNUM,VOLU,1\n";print WFILE "/PNUM,NODE,0\n";print WFILE "/PNUM,TABN,0\n";print WFILE "/PNUM,SVAL,0\n";print WFILE "/NUMBER,0\n";print WFILE "!*\n";print WFILE "/PNUM,ELEM,0\n";print WFILE "/REPLOT\n";print WFILE "VPLOT\n";}188Appendix CMatlab Source Code for TProfile0001 function TProfile(xd, impulse, size I, PD)0002 % xd: length axis in um for impulse response0003 % required step (delta xd) = 0.02um0004 % impulse: temperature (oC) from impulse response as a function of xd0005 % size I: discrete radius (unit 1um) of the impulse response for use in0006 % analysis0007 % PD: power density matrix, unit: mW/um^20008 % Outputs:0009 % - Calculates and plots the temperature profile of the layout0010 % - Plots the impulse response matrix0011 % - Saves the temperature profile in ascii file: tprofile.dat00120013 % Author: Syed M. Alam0014 % Last updated: April 17, 200400150016 %transpose PD for same viewing axis as SysRel0017 PD=PD’;0018 %plot PD;0019 figure;0020 imshow(PD,[min(PD(:)) max(PD(:))]);colorbar;1890021 title(’Power Density (mW/um^2) Profile of the Layout’)0022 xlabel(’x dimension, um’)0023 ylabel(’y dimension, um’)00240025 % create impulse response matrix0026 I=zeros(2*size I+1);0027 center = size I+1;0028 Id=[];0029 % read temperature at 1um offsets upto size I0030 for w=0:size I0031 index = find(xd == w);0032 Id = [Id impulse(index)];0033 end0034 % fill in the I matrix using axi-symmetric property0035 for w=0:size I0036 for y=-w:w0037 I(center-w,center+y)=Id(w+1);0038 I(center+y,center+w)=Id(w+1);0039 I(center+w,center+y)=Id(w+1);0040 I(center+y,center-w)=Id(w+1);0041 end0042 end00430044 % get row and column length of PD0045 [nrow ncol]=size(PD);00460047 % number of elements after convolution in row0048 convlen row = nrow+2*size I+1-1;0049 convlen col = ncol+2*size I+1-1;00501900051 % use pt-point FFT, pt need to be power of 2 for FFT speed0052 pt=2048;0053 if(max(convlen row,convlen col)>pt)0054 disp(’ERROR: PD or I matrix size is greater than FFT points’);0055 return;0056 end00570058 C=ifft2(fft2(PD,pt,pt).*fft2(I,pt,pt));0059 C=C(1:convlen row,1:convlen col);0060 % truncate extra points from 4 sides0061 T=C(size I+1:convlen row-size I,size I+1:convlen col-size I);0062 T=real(T);00630064 %conventional heat sink technology0065 Rth=0.26; %oC/W size 12cmX26cmX10cm with air vol. 0.066m^3/s0066 Tamb = 27; %oC0067 totalP=sum(sum(PD)); %mW0068 Tsub=Tamb+totalP*10^-3*Rth;0069 T=Tsub + T;007000710072 figure;0073 imshow(T,[min(T(:)) max(T(:))]);colorbar;0074 title(’Temperature (^oC) Profile of the Layout’)0075 xlabel(’x dimension, um’)0076 ylabel(’y dimension, um’)00770078 figure;0079 surf(T);colormap(jet);colorbar;0080 title(’Temperature (^oC) Profile of the Layout’)1910081 xlabel(’x dimension, um’)0082 ylabel(’y dimension, um’)0083 zlabel(’temperature (^oC)’)00840085 figure;0086 surf(I);colormap(jet);colorbar0087 title(’Impulse Response Matrix of Temperature (^oC)’)0088 xlabel(’x dimension, um’)0089 ylabel(’y dimension, um’)0090 zlabel(’temperature (^oC)’)00910092 %need to transpose T as power density matrix is transpose0093 T=T’;00940095 save tprofile.dat T -ascii;0096 %fid=fopen(’tprofile.dat’,’w’);0097 %fprintf(fid,’%3.4f ’,T);0098 %fclose(fid);0099 disp(’tprofile.dat file is written with temperature profile matrix’);192Appendix DSysRel ReleaseD.1 SysRel v1.1An internal release of SysRel v1.1 was made at MIT on March 6, 2004. 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