Members of HiPEAC, the European Network of Excellence on High Performance Embedded Architecture and Compilation

D-NUCA caches are on-chip cache memories characterized by multi-bank partitioning and data migration. They exhibit high hit rates while keeping the access latency low. As counterpart, such caches are affected by high static and dynamic power consumption. In this work we present a preliminary power consumption evaluation of a D-NUCA cache. Results show the existing balance among static and dynamic contributions to total power budget