Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling

fkasiar,zeljkogmacs.ece.mcgill.ca In this paper, we consider verification under error-model assumption. We exploit the algebraic properties of the arith-metic transforms that are used in compact graph-based rep-resentations of arithmetic circuits, such as *BMDs. Verifi-cation time can be shortened under assumption of corrupt-ing a bounded number of transform coefficients. Bounds are derived for a number of test vectors, and the vectors suc-cessfully verified arithmetic circuits under a class of error models derived from recently proposed basic design error classes, including single stuck-at faults. 1