Modeling design constraints and biasing in simulation using BDDs

Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulation to a legal input space, while input biasing, which can be considered as a probabilistic constraint, makes it easier to cover interesting “corner ” cases. In this paper, we propose to use constraints and biasing to form a simulation environment instead of using an ex-plicit testbench in hierarchical functional verification. Both con-straints and input biasing can depend on the state of the design and thus are very expressive in modeling the environment. We present a novel method that unifies the handling of constraints and biasing via the use of Binary Decision Diagrams (BDDs). The distribution of input vectors under the effect of constraints and input biasing are determined by what we refer to as the con-strained probabilities. A BDD representing the constraints is first built, then an algorithm is applied to bias the branching probabil-ities in the BDD. During simulation, this annotated BDD is used to generate input vectors whose distribution match their predeter-mined constrained probabilities. The simulation generation is a one-pass process, i.e., no backtracking or retry is needed. Also, we describe a partitioning method to minimize the size of BDDs used in simulation generation. Our techniques were used in the verification of a set of commercial designs; experimental results demonstrated their effectiveness.